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Searched refs:MOV (Results 1 – 25 of 48) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredNeoverse.td60 // MOV Wd, #0
61 // MOV Xd, #0
66 // MOV Wd, WZR
67 // MOV Xd, XZR
68 // MOV Wd, Wn
69 // MOV Xd, Xn
H A DAArch64SchedPredicates.td284 [// MOV {Rd, SP}, {SP, Rn} =>
298 // MOV Rd, Rm =>
H A DAArch64SchedExynosM4.td606 def : InstRW<[M4WriteZ0], (instregex "^MOV[NZ][WX]i")>;
819 def : InstRW<[M4WriteMOVI], (instregex "^(MOV|MVN)I")>;
H A DAArch64SchedExynosM5.td653 def : InstRW<[M5WriteZ0], (instregex "^MOV[NZ][WX]i$")>;
857 def : InstRW<[M5WriteMOVI], (instregex "^(MOV|MVN)I")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrData.td123 def MOV # TYPE.Size # DST_REG # SRC_REG # TYPE.Postfix
130 def MOV # TYPE.Size # dd # TYPE.Postfix
151 def MOV # TYPE.Size # AM # REG # TYPE.Postfix
160 def MOV # TYPE.Size # AM # i # TYPE.Postfix
177 def MOV # TYPE.Size # REG # i # TYPE.Postfix
197 def MOV # TYPE.Size # REG # AM # TYPE.Postfix
207 def MOV # TYPE.Size # REG # AM # _TC
226 def MOV # TYPE.Size # DST_AM # SRC_AM # TYPE.Postfix
545 def MOV#EXT#Xd16d8 : MxPseudoMove_RR<MxType16d, MxType8d>;
546 def MOV#EXT#Xd32d8 : MxPseudoMove_RR<MxType32d, MxType8d>;
[all …]
H A DM68kInstrAtomics.td11 (!cast<MxInst>("MOV"#size#"dj") !cast<MxMemOp>("MxARI"#size):$ptr)>;
14 (!cast<MxInst>("MOV"#size#"jd") !cast<MxMemOp>("MxARI"#size):$ptr,
H A DM68kInstrFormats.td177 // that it's easier for MOV instructions to reverse
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_trampoline_arm.S32 MOV r1, #0
64 MOV r1, #1
97 MOV r1, #1
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp60 buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
67 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV, in copyPhysReg()
90 case R600::MOV: in isMov()
1109 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, in buildIndirectWrite()
1141 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, in buildIndirectRead()
1340 MachineInstr *MovImm = buildDefaultInstruction(BB, I, R600::MOV, DstReg, in buildMovImm()
1349 return buildDefaultInstruction(*MBB, I, R600::MOV, DstReg, SrcReg); in buildMovInstr()
H A DCaymanInstructions.td146 // %t2_x = MOV %zero
H A DR600ISelLowering.cpp244 *BB, I, R600::MOV, MI.getOperand(0).getReg(), in EmitInstrWithCustomInserter()
252 *BB, I, R600::MOV, MI.getOperand(0).getReg(), in EmitInstrWithCustomInserter()
282 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_LITERAL_X); in EmitInstrWithCustomInserter()
293 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_CONST); in EmitInstrWithCustomInserter()
H A DR600Instructions.td788 def MOV : R600_1OP <0x19, "MOV", []>;
H A DEvergreenInstructions.td223 // %t2_x = MOV %zero
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleAtom.td515 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>;
609 "MOV(S|Z)X16rr8",
610 "MOV(UPS|UPD|DQU)mr",
626 "MOV(S|Z)X16rm8",
628 "MOV(UPS|UPD|DQU)rm",
H A DX86SchedAlderlakeP.td561 "^MOV(8|16)rm$",
825 "^MOV(32|64)sr$")>;
1076 def : InstRW<[ADLPWriteResGroup78], (instregex "^(V?)MOV(D|SH|SL)DUPrm$",
1417 def : InstRW<[ADLPWriteResGroup128], (instregex "^MOV(16|32|64)rs$",
1427 def : InstRW<[ADLPWriteResGroup130], (instregex "^MOV(8|32)o(16|32)a$",
1428 "^MOV(8|32|64)o64a$")>;
H A DX86SchedSapphireRapids.td560 "^MOV(8|16)rm$",
934 "^MOV(32|64)sr$")>;
1260 "^(V?)MOV(D|SH|SL)DUPrm$",
1715 def : InstRW<[SPRWriteResGroup137], (instregex "^MOV(8|16|32|64)ri$",
1716 "^MOV(8|16|32)ri_alt$",
1717 "^MOV(8|16)rr((_REV)?)$")>;
1724 def : InstRW<[SPRWriteResGroup138], (instregex "^MOV(16|32|64)rs$",
1734 def : InstRW<[SPRWriteResGroup140], (instregex "^MOV(8|32)o(16|32)a$",
1735 "^MOV(8|32|64)o64a$")>;
H A DX86SchedIceLake.td441 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
669 "(V?)MOV(HL|LH)PS(Z?)rr",
713 "(V?)MOV(SD|SS)(Z?)rr",
H A DX86.td359 // Icelake and newer processors have Fast Short REP MOV.
498 // should be avoided in favor of a MOV + register CALL/PUSH/POP.
/freebsd/contrib/file/magic/Magdir/
H A Dfilesystems563 …3rd sector of MS x86 bootloader with assembler instructions cli;MOVZX EAX,BYTE PTR [BP+10];MOV ECX,
1266 # for 1st version assembler instructions: cld;xor ax,ax;mov DS,ax;MOV ES,AX;mov SI,
1904 # assembler instructions: CLI;MOV SP,1E7;MOV AX;07c0;MOV
1913 # assembler instructions: CLI;MOV AX,CS;MOV DS,AX;MOV DX,0
1920 # assembler instructions: CLI;MOV AX,CS;MOV DS,AX;XOR DX,DX;MOV
1927 # assembler instructions: MOV BX,07c0;MOV SS,BX;MOV SP,01c6
1932 # assembler instructions: MOV AX,CS;MOV DS,AX;CLI;MOV SS,AX;
1936 # assembler instructions: CLI;PUSH CS;POP SS;MOV SP,7c00;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td83 def : M4UnitL1I<(instregex "(t|t2)MOV")>;
H A DARMScheduleA57.td212 // MOV{S}, MOVW, MVN{S}
213 def : InstRW<[A57Write_1cyc_1I], (instregex "MOV(r|i|i16|r_TC)",
224 def : InstRW<[A57WriteMOVsi], (instregex "MOV(CC)?si", "MVNsi",
235 def : InstRW<[A57WriteMOVsr], (instregex "MOV(CC)?sr", "MVNsr", "t2MVNs",
H A DARMScheduleSwift.td155 // MOV(register-shiftedregister) MVN(register-shiftedregister)
157 // MOV,MVN
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaOperands.td47 // imm12m predicate - Immediate for MOV operation
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrInfo.td365 // MOV instruction and variants (conditional mov).
775 // Compact MOV/ADD/CMP Immediate instructions.
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp2434 auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr) in expand() local
2438 MOV->getOperand(1).setIsKill(); in expand()

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