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Searched refs:MOI (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DStackMaps.cpp207 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI, in parseOperand() argument
211 if (MOI->isImm()) { in parseOperand()
212 switch (MOI->getImm()) { in parseOperand()
221 Register Reg = (++MOI)->getReg(); in parseOperand()
222 int64_t Imm = (++MOI)->getImm(); in parseOperand()
228 int64_t Size = (++MOI)->getImm(); in parseOperand()
230 Register Reg = (++MOI)->getReg(); in parseOperand()
231 int64_t Imm = (++MOI)->getImm(); in parseOperand()
237 ++MOI; in parseOperand()
238 assert(MOI->isImm() && "Expected constant operand."); in parseOperand()
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H A DLiveInterval.cpp893 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) { in stripValuesNotDefiningMask() local
894 if (!MOI->isReg() || !MOI->isDef()) in stripValuesNotDefiningMask()
896 if (MOI->getReg() != Reg) in stripValuesNotDefiningMask()
898 LaneBitmask OrigMask = TRI.getSubRegIndexLaneMask(MOI->getSubReg()); in stripValuesNotDefiningMask()
H A DMachineVerifier.cpp3604 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) { in verifyLiveRangeValue() local
3605 if (!MOI->isReg() || !MOI->isDef()) in verifyLiveRangeValue()
3608 if (MOI->getReg() != VRegOrUnit.asVirtualReg()) in verifyLiveRangeValue()
3611 if (!MOI->getReg().isPhysical() || in verifyLiveRangeValue()
3612 !TRI->hasRegUnit(MOI->getReg(), VRegOrUnit.asMCRegUnit())) in verifyLiveRangeValue()
3616 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none()) in verifyLiveRangeValue()
3619 if (MOI->isEarlyClobber()) in verifyLiveRangeValue()
3744 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) { in verifyLiveRangeSegment() local
3745 if (!MOI->isReg() || MOI->getReg() != VRegOrUnit.asVirtualReg()) in verifyLiveRangeSegment()
3747 unsigned Sub = MOI->getSubReg(); in verifyLiveRangeSegment()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp651 bool expandLoad(const SIMemOpInfo &MOI,
655 bool expandStore(const SIMemOpInfo &MOI,
659 bool expandAtomicFence(const SIMemOpInfo &MOI,
663 bool expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI,
2602 bool SIMemoryLegalizer::expandLoad(const SIMemOpInfo &MOI, in expandLoad() argument
2608 if (MOI.isAtomic()) { in expandLoad()
2609 const AtomicOrdering Order = MOI.getOrdering(); in expandLoad()
2613 Changed |= CC->enableLoadCacheBypass(MI, MOI.getScope(), in expandLoad()
2614 MOI.getOrderingAddrSpace()); in expandLoad()
2618 Changed |= CC->insertWait(MI, MOI.getScope(), MOI.getOrderingAddrSpace(), in expandLoad()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp103 const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo]; in printOperand() local
104 if (MOI.RegClass == AVR::ZREGRegClassID) { in printOperand()
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
126 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DStackMaps.h368 parseOperand(MachineInstr::const_mop_iterator MOI,
375 MachineInstr::const_mop_iterator MOI,
396 MachineInstr::const_mop_iterator MOI,
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp715 MachineInstr::mop_iterator MOI = MI->operands_begin(); in predicateInstr() local
717 MIB.add(*MOI); in predicateInstr()
718 ++MOI; in predicateInstr()
721 for (const MachineOperand &MO : make_range(MOI, MI->operands_end())) in predicateInstr()