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Searched refs:MI (Results 1 – 25 of 1200) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h53 MachineInstr *MI; member
180 bool tryCombineCopy(MachineInstr &MI) const;
181 bool matchCombineCopy(MachineInstr &MI) const;
182 void applyCombineCopy(MachineInstr &MI) const;
199 bool tryCombineExtendingLoads(MachineInstr &MI) const;
200 bool matchCombineExtendingLoads(MachineInstr &MI,
202 void applyCombineExtendingLoads(MachineInstr &MI,
206 bool matchCombineLoadWithAndMask(MachineInstr &MI,
211 bool matchCombineExtractedVectorLoad(MachineInstr &MI,
214 bool matchCombineIndexedLoadStore(MachineInstr &MI,
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H A DLegalizerHelper.h96 LLVM_ABI LegalizeResult legalizeInstrStep(MachineInstr &MI,
100 LLVM_ABI LegalizeResult libcall(MachineInstr &MI,
105 LLVM_ABI LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx,
111 LLVM_ABI LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx,
115 LLVM_ABI LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
119 LLVM_ABI LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
123 LLVM_ABI LegalizeResult fewerElementsVector(MachineInstr &MI,
128 LLVM_ABI LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
142 LLVM_ABI void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
148 LLVM_ABI void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
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H A DGenericMachineInstrs.h40 static bool classof(const MachineInstr *MI) { in classof() argument
41 return isPreISelGenericOpcode(MI->getOpcode()); in classof()
77 static bool classof(const MachineInstr *MI) { in classof() argument
78 return GenericMachineInstr::classof(MI) && MI->hasOneMemOperand(); in classof()
89 static bool classof(const MachineInstr *MI) { in classof() argument
90 switch (MI->getOpcode()) { in classof()
119 static bool classof(const MachineInstr *MI) { in classof() argument
120 return MI->getOpcode() == TargetOpcode::G_INDEXED_LOAD; in classof()
127 static bool classof(const MachineInstr *MI) { in classof() argument
128 return MI->getOpcode() == TargetOpcode::G_INDEXED_SEXTLOAD || in classof()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp38 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
39 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
40 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
41 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
42 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
43 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
44 bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);
65 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
66 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 && in tieOpsIfNeeded()
67 !MI.getOperand(0).isTied()) in tieOpsIfNeeded()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kInstPrinter.h34 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
38 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
41 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
42 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
46 getMnemonic(const MCInst &MI) const override;
49 void printOperand(const MCInst *MI, unsigned opNum, raw_ostream &O);
50 void printImmediate(const MCInst *MI, unsigned opNum, raw_ostream &O);
52 void printMoveMask(const MCInst *MI, unsigned opNum, raw_ostream &O);
54 void printMoveMaskR(const MCInst *MI, unsigned opNum, raw_ostream &O);
55 void printDisp(const MCInst *MI, unsigned opNum, raw_ostream &O);
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h57 Register isLoadFromStackSlot(const MachineInstr &MI,
65 Register isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
205 bool expandPostRAPseudo(MachineInstr &MI) const override;
221 MachineBasicBlock::iterator MI) const override;
224 bool isPredicated(const MachineInstr &MI) const override;
227 bool isPostIncrement(const MachineInstr &MI) const override;
231 bool PredicateInstruction(MachineInstr &MI,
242 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp61 void XtensaInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
64 printInstruction(MI, Address, O); in printInst()
72 void XtensaInstPrinter::printOperand(const MCInst *MI, int OpNum, in printOperand() argument
74 printOperand(MI->getOperand(OpNum), O); in printOperand()
77 void XtensaInstPrinter::printMemOperand(const MCInst *MI, int OpNum, in printMemOperand() argument
79 OS << getRegisterName(MI->getOperand(OpNum).getReg()); in printMemOperand()
81 printOperand(MI, OpNum + 1, OS); in printMemOperand()
84 void XtensaInstPrinter::printBranchTarget(const MCInst *MI, uint64_t Address, in printBranchTarget() argument
86 const MCOperand &MC = MI->getOperand(OpNum); in printBranchTarget()
87 if (MI->getOperand(OpNum).isImm()) { in printBranchTarget()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86IntelInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
30 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
34 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
35 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
41 getMnemonic(const MCInst &MI) const override;
42 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
45 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) override;
46 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
47 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
48 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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H A DX86ATTInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
30 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
34 bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
35 void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
41 getMnemonic(const MCInst &MI) const override;
42 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &OS);
45 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
46 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
47 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
48 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
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H A DX86InstComments.cpp270 static unsigned getRegOperandNumElts(const MCInst *MI, unsigned ScalarSize, in getRegOperandNumElts() argument
272 MCRegister OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
281 static void printMasking(raw_ostream &OS, const MCInst *MI, in printMasking() argument
283 const MCInstrDesc &Desc = MCII.get(MI->getOpcode()); in printMasking()
295 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
305 static bool printFMAComments(const MCInst *MI, raw_ostream &OS, in printFMAComments() argument
308 unsigned NumOperands = MI->getNumOperands(); in printFMAComments()
327 switch (MI->getOpcode()) { in printFMAComments()
333 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
337 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp35 bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument
39 printOperand(MI, OpNo0, OS); in printInst()
41 printOperand(MI, OpNo1, OS); in printInst()
45 static bool usesGivenOffset(const MCInst *MI, int AddOffset) { in usesGivenOffset() argument
46 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
48 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
49 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
52 static bool isPreIncrementForm(const MCInst *MI, int AddOffset) { in isPreIncrementForm() argument
53 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
54 return LPAC::isPreOp(AluCode) && usesGivenOffset(MI, AddOffset); in isPreIncrementForm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h58 static inline bool isVCTP(const MachineInstr *MI) { in isVCTP() argument
59 switch (MI->getOpcode()) { in isVCTP()
71 static inline bool isDoLoopStart(const MachineInstr &MI) { in isDoLoopStart() argument
72 return MI.getOpcode() == ARM::t2DoLoopStart || in isDoLoopStart()
73 MI.getOpcode() == ARM::t2DoLoopStartTP; in isDoLoopStart()
76 static inline bool isWhileLoopStart(const MachineInstr &MI) { in isWhileLoopStart() argument
77 return MI.getOpcode() == ARM::t2WhileLoopStart || in isWhileLoopStart()
78 MI.getOpcode() == ARM::t2WhileLoopStartLR || in isWhileLoopStart()
79 MI.getOpcode() == ARM::t2WhileLoopStartTP; in isWhileLoopStart()
82 static inline bool isLoopStart(const MachineInstr &MI) { in isLoopStart() argument
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H A DARMLowOverheadLoops.cpp86 static bool isVectorPredicated(MachineInstr *MI) { in isVectorPredicated() argument
87 int PIdx = llvm::findFirstVPTPredOperandIdx(*MI); in isVectorPredicated()
88 return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR; in isVectorPredicated()
91 static bool isVectorPredicate(MachineInstr *MI) { in isVectorPredicate() argument
92 return MI->findRegisterDefOperandIdx(ARM::VPR, /*TRI=*/nullptr) != -1; in isVectorPredicate()
95 static bool hasVPRUse(MachineInstr &MI) { in hasVPRUse() argument
96 return MI.findRegisterUseOperandIdx(ARM::VPR, /*TRI=*/nullptr) != -1; in hasVPRUse()
99 static bool isDomainMVE(MachineInstr *MI) { in isDomainMVE() argument
100 uint64_t Domain = MI->getDesc().TSFlags & ARMII::DomainMask; in isDomainMVE()
104 static int getVecSize(const MachineInstr &MI) { in getVecSize() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h28 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
34 getMnemonic(const MCInst &MI) const override;
35 void printInstruction(const MCInst *MI, uint64_t Address,
37 virtual bool printAliasInstr(const MCInst *MI, uint64_t Address,
39 virtual void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
46 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
48 void printOperand(const MCInst *MI, uint64_t Address, unsigned OpNum,
51 void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
53 void printSORegImmOperand(const MCInst *MI, unsigned OpNum,
56 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() argument
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
34 return MI.getOperand(OpNo).getReg() == R; in isReg()
80 void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
83 switch (MI->getOpcode()) { in printInst()
93 printSaveRestore(MI, STI, O); in printInst()
98 printSaveRestore(MI, STI, O); in printInst()
103 printSaveRestore(MI, STI, O); in printInst()
108 printSaveRestore(MI, STI, O); in printInst()
114 if (!printAliasInstr(MI, Address, STI, O) && in printInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp76 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { in EmitInstruction() argument
77 CurrCycleInstr = MI; in EmitInstruction()
120 const MachineInstr &MI) { in isSendMsgTraceDataOrGDS() argument
121 if (TII.isAlwaysGDS(MI.getOpcode())) in isSendMsgTraceDataOrGDS()
124 switch (MI.getOpcode()) { in isSendMsgTraceDataOrGDS()
135 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
136 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in isSendMsgTraceDataOrGDS()
138 if (MI.getOperand(GDS).getImm()) in isSendMsgTraceDataOrGDS()
145 static bool isPermlane(const MachineInstr &MI) { in isPermlane() argument
146 unsigned Opcode = MI.getOpcode(); in isPermlane()
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H A DSIMemoryLegalizer.cpp225 void reportUnsupported(const MachineBasicBlock::iterator &MI,
241 constructFromMIWithMMO(const MachineBasicBlock::iterator &MI) const;
250 getLoadInfo(const MachineBasicBlock::iterator &MI) const;
255 getStoreInfo(const MachineBasicBlock::iterator &MI) const;
260 getAtomicFenceInfo(const MachineBasicBlock::iterator &MI) const;
265 getAtomicCmpxchgOrRmwInfo(const MachineBasicBlock::iterator &MI) const;
286 bool enableNamedBit(const MachineBasicBlock::iterator MI,
297 virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
304 virtual bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
311 virtual bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
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H A DSIInstrInfo.h54 void insert(MachineInstr *MI);
73 bool isDeferred(MachineInstr *MI);
109 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
116 MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI,
181 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
183 bool verifyCopy(const MachineInstr &MI, const MachineRegisterInfo &MRI,
186 bool resultDependsOnExec(const MachineInstr &MI) const;
193 isCopyInstrImpl(const MachineInstr &MI) const override;
195 bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0,
198 bool isLegalToSwap(const MachineInstr &MI, unsigned fromIdx,
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H A DAMDGPULegalizerInfo.h37 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
58 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVInstPrinter.cpp32 void SPIRVInstPrinter::printRemainingVariableOps(const MCInst *MI, in printRemainingVariableOps() argument
37 const unsigned NumOps = MI->getNumOperands(); in printRemainingVariableOps()
39 if (!SkipImmediates || !MI->getOperand(i).isImm()) { in printRemainingVariableOps()
42 printOperand(MI, i, O); in printRemainingVariableOps()
47 void SPIRVInstPrinter::printOpConstantVarOps(const MCInst *MI, in printOpConstantVarOps() argument
50 unsigned IsBitwidth16 = MI->getFlags() & SPIRV::INST_PRINTER_WIDTH16; in printOpConstantVarOps()
51 const unsigned NumVarOps = MI->getNumOperands() - StartIndex; in printOpConstantVarOps()
58 uint64_t Imm = MI->getOperand(StartIndex).getImm(); in printOpConstantVarOps()
62 Imm |= (MI->getOperand(StartIndex + 1).getImm() << 32); in printOpConstantVarOps()
66 if (MI->getOpcode() == SPIRV::OpConstantF && IsBitwidth16 == 0) { in printOpConstantVarOps()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp40 void VEInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
43 if (!printAliasInstr(MI, Address, STI, OS)) in printInst()
44 printInstruction(MI, Address, STI, OS); in printInst()
48 void VEInstPrinter::printOperand(const MCInst *MI, int OpNum, in printOperand() argument
50 const MCOperand &MO = MI->getOperand(OpNum); in printOperand()
68 void VEInstPrinter::printMemASXOperand(const MCInst *MI, int OpNum, in printMemASXOperand() argument
71 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
72 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
75 printOperand(MI, OpNum + 2, STI, O); in printMemASXOperand()
77 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h28 getMnemonic(const MCInst &MI) const override;
29 void printInstruction(const MCInst *MI, uint64_t Address,
34 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
40 void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
42 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
45 void printFP64ImmOperand(const MCInst *MI, unsigned OpNo,
47 void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
49 void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
51 void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCBranchFinalize.cpp51 void replaceWithBRcc(MachineInstr *MI) const;
52 void replaceWithCmpBcc(MachineInstr *MI) const;
95 static bool isBRccPseudo(MachineInstr *MI) { in isBRccPseudo() argument
96 return !(MI->getOpcode() != ARC::BRcc_rr_p && in isBRccPseudo()
97 MI->getOpcode() != ARC::BRcc_ru6_p); in isBRccPseudo()
100 static unsigned getBRccForPseudo(MachineInstr *MI) { in getBRccForPseudo() argument
101 assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction."); in getBRccForPseudo()
102 if (MI->getOpcode() == ARC::BRcc_rr_p) in getBRccForPseudo()
107 static unsigned getCmpForPseudo(MachineInstr *MI) { in getCmpForPseudo() argument
108 assert(isBRccPseudo(MI) && "Can't get BRcc for wrong instruction."); in getCmpForPseudo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp117 bool splitTwoPartImm(MachineInstr &MI,
120 bool checkMovImmInstr(MachineInstr &MI, MachineInstr *&MovMI,
124 bool visitADDSUB(unsigned PosOpc, unsigned NegOpc, MachineInstr &MI);
126 bool visitADDSSUBS(OpcodePair PosOpcs, OpcodePair NegOpcs, MachineInstr &MI);
129 bool visitAND(unsigned Opc, MachineInstr &MI);
130 bool visitORR(MachineInstr &MI);
131 bool visitCSEL(MachineInstr &MI);
132 bool visitINSERT(MachineInstr &MI);
133 bool visitINSviGPR(MachineInstr &MI, unsigned Opc);
134 bool visitINSvi64lane(MachineInstr &MI);
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.cpp56 void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address, in printInst() argument
64 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) && in printInst()
65 MI->getOperand(2).isExpr()) { in printInst()
66 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) && in printInst()
70 assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) && in printInst()
75 printOperand(MI, 0, STI, O); in printInst()
77 printOperand(MI, 2, STI, O); in printInst()
79 printOperand(MI, 1, STI, O); in printInst()
87 unsigned LastOp = MI->getNumOperands() - 1; in printInst()
88 if (MI->getNumOperands() > 1) { in printInst()
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