Lines Matching refs:MI

57   Register isLoadFromStackSlot(const MachineInstr &MI,
65 Register isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
205 bool expandPostRAPseudo(MachineInstr &MI) const override;
221 MachineBasicBlock::iterator MI) const override;
224 bool isPredicated(const MachineInstr &MI) const override;
227 bool isPostIncrement(const MachineInstr &MI) const override;
231 bool PredicateInstruction(MachineInstr &MI,
242 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
248 bool isPredicable(const MachineInstr &MI) const override;
252 bool isSchedulingBoundary(const MachineInstr &MI,
273 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
281 const MachineInstr &MI,
298 bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
302 bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
339 bool isTailCall(const MachineInstr &MI) const override;
340 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
346 bool shouldSink(const MachineInstr &MI) const override;
355 bool isAbsoluteSet(const MachineInstr &MI) const;
356 bool isAccumulator(const MachineInstr &MI) const;
357 bool isAddrModeWithOffset(const MachineInstr &MI) const;
358 bool isBaseImmOffset(const MachineInstr &MI) const;
359 bool isComplex(const MachineInstr &MI) const;
360 bool isCompoundBranchInstr(const MachineInstr &MI) const;
361 bool isConstExtended(const MachineInstr &MI) const;
362 bool isDeallocRet(const MachineInstr &MI) const;
365 bool isDotCurInst(const MachineInstr &MI) const;
366 bool isDotNewInst(const MachineInstr &MI) const;
370 bool isExtendable(const MachineInstr &MI) const;
371 bool isExtended(const MachineInstr &MI) const;
372 bool isFloat(const MachineInstr &MI) const;
375 bool isIndirectCall(const MachineInstr &MI) const;
376 bool isIndirectL4Return(const MachineInstr &MI) const;
377 bool isJumpR(const MachineInstr &MI) const;
378 bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
379 bool isLateSourceInstr(const MachineInstr &MI) const;
380 bool isLoopN(const MachineInstr &MI) const;
381 bool isMemOp(const MachineInstr &MI) const;
382 bool isNewValue(const MachineInstr &MI) const;
384 bool isNewValueInst(const MachineInstr &MI) const;
385 bool isNewValueJump(const MachineInstr &MI) const;
387 bool isNewValueStore(const MachineInstr &MI) const;
389 bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
390 bool isPredicatedNew(const MachineInstr &MI) const;
392 bool isPredicatedTrue(const MachineInstr &MI) const;
397 bool isPureSlot0(const MachineInstr &MI) const;
398 bool isRestrictNoSlot1Store(const MachineInstr &MI) const;
399 bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
400 bool isSignExtendingLoad(const MachineInstr &MI) const;
401 bool isSolo(const MachineInstr &MI) const;
402 bool isSpillPredRegOp(const MachineInstr &MI) const;
403 bool isTC1(const MachineInstr &MI) const;
404 bool isTC2(const MachineInstr &MI) const;
405 bool isTC2Early(const MachineInstr &MI) const;
406 bool isTC4x(const MachineInstr &MI) const;
409 bool isHVXVec(const MachineInstr &MI) const;
413 bool isVecAcc(const MachineInstr &MI) const;
414 bool isVecALU(const MachineInstr &MI) const;
417 bool isZeroExtendingLoad(const MachineInstr &MI) const;
425 bool hasNonExtEquivalent(const MachineInstr &MI) const;
426 bool hasPseudoInstrPair(const MachineInstr &MI) const;
428 bool mayBeCurLoad(const MachineInstr &MI) const;
429 bool mayBeNewStore(const MachineInstr &MI) const;
432 bool producesStall(const MachineInstr &MI,
434 bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const;
438 unsigned getAddrMode(const MachineInstr &MI) const;
439 MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
442 unsigned getCExtOpNum(const MachineInstr &MI) const;
444 getCompoundCandidateGroup(const MachineInstr &MI) const;
447 int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore = true) const;
449 int getDotCurOp(const MachineInstr &MI) const;
450 int getNonDotCurOp(const MachineInstr &MI) const;
451 int getDotNewOp(const MachineInstr &MI) const;
452 int getDotNewPredJumpOp(const MachineInstr &MI,
454 int getDotNewPredOp(const MachineInstr &MI,
456 int getDotOldOp(const MachineInstr &MI) const;
457 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
459 short getEquivalentHWInstr(const MachineInstr &MI) const;
461 const MachineInstr &MI) const;
464 int getMaxValue(const MachineInstr &MI) const;
465 unsigned getMemAccessSize(const MachineInstr &MI) const;
466 int getMinValue(const MachineInstr &MI) const;
467 short getNonExtOpcode(const MachineInstr &MI) const;
470 short getPseudoInstrPair(const MachineInstr &MI) const;
471 short getRegForm(const MachineInstr &MI) const;
472 unsigned getSize(const MachineInstr &MI) const;
473 uint64_t getType(const MachineInstr &MI) const;
474 InstrStage::FuncUnits getUnits(const MachineInstr &MI) const;
476 MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const;
483 void immediateExtend(MachineInstr &MI) const;
484 bool invertAndChangeJumpTarget(MachineInstr &MI,
487 bool reversePredSense(MachineInstr &MI) const;
514 short changeAddrMode_abs_io(const MachineInstr &MI) const { in changeAddrMode_abs_io() argument
515 return changeAddrMode_abs_io(MI.getOpcode()); in changeAddrMode_abs_io()
517 short changeAddrMode_io_abs(const MachineInstr &MI) const { in changeAddrMode_io_abs() argument
518 return changeAddrMode_io_abs(MI.getOpcode()); in changeAddrMode_io_abs()
520 short changeAddrMode_io_rr(const MachineInstr &MI) const { in changeAddrMode_io_rr() argument
521 return changeAddrMode_io_rr(MI.getOpcode()); in changeAddrMode_io_rr()
523 short changeAddrMode_rr_io(const MachineInstr &MI) const { in changeAddrMode_rr_io() argument
524 return changeAddrMode_rr_io(MI.getOpcode()); in changeAddrMode_rr_io()
526 short changeAddrMode_rr_ur(const MachineInstr &MI) const { in changeAddrMode_rr_ur() argument
527 return changeAddrMode_rr_ur(MI.getOpcode()); in changeAddrMode_rr_ur()
529 short changeAddrMode_ur_rr(const MachineInstr &MI) const { in changeAddrMode_ur_rr() argument
530 return changeAddrMode_ur_rr(MI.getOpcode()); in changeAddrMode_ur_rr()