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Searched refs:MFOCRF (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBack2BackFusion.def113 MFOCRF,
643 MFOCRF,
H A DPPCRegisterInfo.cpp977 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRSpilling()
1140 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRBitSpilling()
1195 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) in lowerCRBitRestore()
H A DPPCISelLowering.h218 MFOCRF, enumerator
H A DPPC.td92 "Enable the MFOCRF instruction">;
H A DPPCAsmPrinter.cpp1563 case PPC::MFOCRF: in emitInstruction()
1569 MI->getOpcode() == PPC::MFOCRF ? PPC::MFCR : PPC::MFCR8; in emitInstruction()
H A DP10InstrResources.td909 MFOCRF, MFOCRF8,
H A DPPCISelDAGToDAG.cpp4615 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, in trySETCC()
5417 SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR6Reg, in Select()
5516 case PPCISD::MFOCRF: { in Select()
5518 ReplaceNode(N, CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, in Select()
H A DPPCInstrInfo.cpp1708 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); in copyPhysReg()
1722 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF; in copyPhysReg()
H A DPPCISelLowering.cpp1735 case PPCISD::MFOCRF: return "PPCISD::MFOCRF"; in getTargetNodeName()
11534 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
17331 if (FlagUser->getOpcode() == PPCISD::MFOCRF) in PerformDAGCombine()
H A DPPCInstrInfo.td2822 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM),
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp458 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && in get_crbitm_encoding()
485 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || in getMachineOpValue()