Searched refs:MFOCRF (Results 1 – 11 of 11) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 463 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && 487 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. 490 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCBack2BackFusion.def | 113 MFOCRF, 643 MFOCRF,
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H A D | PPCRegisterInfo.cpp | 974 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRSpilling() 1132 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRBitSpilling() 1187 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) in lowerCRBitRestore()
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H A D | PPCISelLowering.h | 215 MFOCRF, enumerator
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H A D | PPC.td | 92 "Enable the MFOCRF instruction">;
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H A D | PPCAsmPrinter.cpp | 1584 case PPC::MFOCRF: in emitInstruction() 1590 MI->getOpcode() == PPC::MFOCRF ? PPC::MFCR : PPC::MFCR8; in emitInstruction()
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H A D | P10InstrResources.td | 907 MFOCRF, MFOCRF8,
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H A D | PPCISelDAGToDAG.cpp | 4616 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, in trySETCC() 5403 SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR6Reg, in Select() 5503 case PPCISD::MFOCRF: { in Select() 5505 ReplaceNode(N, CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, in Select()
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H A D | PPCInstrInfo.cpp | 1709 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); in copyPhysReg() 1723 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF; in copyPhysReg()
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H A D | PPCISelLowering.cpp | 1737 case PPCISD::MFOCRF: return "PPCISD::MFOCRF"; in getTargetNodeName() 11133 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN() 16439 if (FlagUser->getOpcode() == PPCISD::MFOCRF) in PerformDAGCombine()
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H A D | PPCInstrInfo.td | 2794 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM),
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