Searched refs:MFENCE (Results 1 – 15 of 15) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCA/ |
| H A D | X86CustomBehaviour.cpp | 26 case X86::MFENCE: in setMemBarriers()
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| /freebsd/sys/x86/linux/ |
| H A D | linux_vdso_gettc_x86.inc | 109 [1] = { /* AMD, MFENCE */
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 386 if (MI.getOpcode() == X86::MFENCE) in hasVulnerableLoad()
1319 if (MI.getOpcode() == X86::MFENCE) in tracePredStateThroughBlocksAndHarden()
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| H A D | X86LoadValueInjectionLoadHardening.cpp | 768 if (!MI.mayLoadOrStore() || MI.getOpcode() == X86::MFENCE || in instrUsesRegToAccessMemory()
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| H A D | X86ISelLowering.h | 674 MFENCE, enumerator
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| H A D | X86InstrFragments.td | 139 def X86MFence : SDNode<"X86ISD::MFENCE", SDTNone, [SDNPHasChain]>;
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| H A D | X86SchedBroadwell.td | 720 MFENCE,
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| H A D | X86SchedSkylakeClient.td | 840 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
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| H A D | X86SchedHaswell.td | 1117 MFENCE,
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| H A D | X86SchedAlderlakeP.td | 690 MFENCE)>;
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| H A D | X86SchedSkylakeServer.td | 902 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
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| H A D | X86SchedIceLake.td | 917 def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>;
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| H A D | X86SchedSapphireRapids.td | 769 MFENCE)>;
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| H A D | X86InstrSSE.td | 3260 def MFENCE : I<0xAE, MRM6X, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>,
3264 def : Pat<(X86MFence), (MFENCE)>;
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| H A D | X86ISelLowering.cpp | 31063 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); in LowerATOMIC_FENCE()
33884 NODE_NAME_CASE(MFENCE) in getTargetNodeName()
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