104eeddc0SDimitry Andric //===------------------- X86CustomBehaviour.cpp -----------------*-C++ -* -===// 204eeddc0SDimitry Andric // 304eeddc0SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 404eeddc0SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 504eeddc0SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 604eeddc0SDimitry Andric // 704eeddc0SDimitry Andric //===----------------------------------------------------------------------===// 804eeddc0SDimitry Andric /// \file 904eeddc0SDimitry Andric /// 1004eeddc0SDimitry Andric /// This file implements methods from the X86CustomBehaviour class. 1104eeddc0SDimitry Andric /// 1204eeddc0SDimitry Andric //===----------------------------------------------------------------------===// 1304eeddc0SDimitry Andric 1404eeddc0SDimitry Andric #include "X86CustomBehaviour.h" 1504eeddc0SDimitry Andric #include "TargetInfo/X86TargetInfo.h" 16*5f757f3fSDimitry Andric #include "MCTargetDesc/X86BaseInfo.h" 1704eeddc0SDimitry Andric #include "llvm/MC/TargetRegistry.h" 1804eeddc0SDimitry Andric #include "llvm/Support/WithColor.h" 1904eeddc0SDimitry Andric 2004eeddc0SDimitry Andric namespace llvm { 2104eeddc0SDimitry Andric namespace mca { 2204eeddc0SDimitry Andric 2304eeddc0SDimitry Andric void X86InstrPostProcess::setMemBarriers(std::unique_ptr<Instruction> &Inst, 2404eeddc0SDimitry Andric const MCInst &MCI) { 2504eeddc0SDimitry Andric switch (MCI.getOpcode()) { 2604eeddc0SDimitry Andric case X86::MFENCE: 2704eeddc0SDimitry Andric Inst->setLoadBarrier(true); 2804eeddc0SDimitry Andric Inst->setStoreBarrier(true); 2904eeddc0SDimitry Andric break; 3004eeddc0SDimitry Andric case X86::LFENCE: 3104eeddc0SDimitry Andric Inst->setLoadBarrier(true); 3204eeddc0SDimitry Andric break; 3304eeddc0SDimitry Andric case X86::SFENCE: 3404eeddc0SDimitry Andric Inst->setStoreBarrier(true); 3504eeddc0SDimitry Andric break; 3604eeddc0SDimitry Andric } 3704eeddc0SDimitry Andric } 3804eeddc0SDimitry Andric 3904eeddc0SDimitry Andric void X86InstrPostProcess::postProcessInstruction( 4004eeddc0SDimitry Andric std::unique_ptr<Instruction> &Inst, const MCInst &MCI) { 4104eeddc0SDimitry Andric // Currently, we only modify certain instructions' IsALoadBarrier and 4204eeddc0SDimitry Andric // IsAStoreBarrier flags. 4304eeddc0SDimitry Andric setMemBarriers(Inst, MCI); 4404eeddc0SDimitry Andric } 4504eeddc0SDimitry Andric 4604eeddc0SDimitry Andric } // namespace mca 4704eeddc0SDimitry Andric } // namespace llvm 4804eeddc0SDimitry Andric 4904eeddc0SDimitry Andric using namespace llvm; 5004eeddc0SDimitry Andric using namespace mca; 5104eeddc0SDimitry Andric 5204eeddc0SDimitry Andric static InstrPostProcess *createX86InstrPostProcess(const MCSubtargetInfo &STI, 5304eeddc0SDimitry Andric const MCInstrInfo &MCII) { 5404eeddc0SDimitry Andric return new X86InstrPostProcess(STI, MCII); 5504eeddc0SDimitry Andric } 5604eeddc0SDimitry Andric 5704eeddc0SDimitry Andric /// Extern function to initialize the targets for the X86 backend 5804eeddc0SDimitry Andric 5904eeddc0SDimitry Andric extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMCA() { 6004eeddc0SDimitry Andric TargetRegistry::RegisterInstrPostProcess(getTheX86_32Target(), 6104eeddc0SDimitry Andric createX86InstrPostProcess); 6204eeddc0SDimitry Andric TargetRegistry::RegisterInstrPostProcess(getTheX86_64Target(), 6304eeddc0SDimitry Andric createX86InstrPostProcess); 6404eeddc0SDimitry Andric } 65