Home
last modified time | relevance | path

Searched refs:MCOperand (Results 1 – 25 of 189) sorted by relevance

12345678

/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp71 static MCOperand createVEMCOperand(VEMCExpr::VariantKind Kind, MCSymbol *Sym, in createVEMCOperand()
75 return MCOperand::createExpr(expr); in createVEMCOperand()
78 static MCOperand createGOTRelExprOp(VEMCExpr::VariantKind Kind, in createGOTRelExprOp()
82 return MCOperand::createExpr(expr); in createGOTRelExprOp()
85 static void emitSIC(MCStreamer &OutStreamer, MCOperand &RD, in emitSIC()
93 static void emitBSIC(MCStreamer &OutStreamer, MCOperand &R1, MCOperand &R2, in emitBSIC()
99 MCOperand czero = MCOperand::createImm(0); in emitBSIC()
105 static void emitLEAzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, in emitLEAzzi()
110 MCOperand CZero = MCOperand::createImm(0); in emitLEAzzi()
117 static void emitLEASLzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, in emitLEASLzzi()
[all …]
H A DVEMCInstLower.cpp28 static MCOperand LowerSymbolOperand(const MachineInstr *MI, in LowerSymbolOperand()
40 return MCOperand::createExpr(Expr); in LowerSymbolOperand()
43 static MCOperand LowerOperand(const MachineInstr *MI, const MachineOperand &MO, in LowerOperand()
52 return MCOperand::createReg(MO.getReg()); in LowerOperand()
65 return MCOperand::createImm(MO.getImm()); in LowerOperand()
74 return MCOperand(); in LowerOperand()
82 MCOperand MCOp = LowerOperand(MI, MO, AP); in LowerVEMachineInstrToMCInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp563 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
569 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
580 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
584 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
594 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
596 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
598 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
632 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
635 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp74 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
79 return MCOperand::createExpr(expr); in createSparcMCOperand()
82 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
87 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
102 return MCOperand::createExpr(expr); in createPCXRelExprOp()
106 MCOperand &Callee, in EmitCall()
115 static void EmitRDPC(MCStreamer &OutStreamer, MCOperand &RD, in EmitRDPC()
120 RDPCInst.addOperand(MCOperand::createReg(SP::ASR5)); in EmitRDPC()
125 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
136 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
[all …]
H A DSparcMCInstLower.cpp29 static MCOperand LowerSymbolOperand(const MachineInstr *MI, in LowerSymbolOperand()
64 return MCOperand::createExpr(expr); in LowerSymbolOperand()
67 static MCOperand LowerOperand(const MachineInstr *MI, in LowerOperand()
75 return MCOperand::createReg(MO.getReg()); in LowerOperand()
78 return MCOperand::createImm(MO.getImm()); in LowerOperand()
90 return MCOperand(); in LowerOperand()
101 MCOperand MCOp = LowerOperand(MI, MO, AP); in LowerSparcMachineInstrToMCInst()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInst.h36 class MCOperand {
58 MCOperand() : FPImmVal(0) {} in MCOperand() function
134 static MCOperand createReg(unsigned Reg) { in createReg()
135 MCOperand Op; in createReg()
141 static MCOperand createImm(int64_t Val) { in createImm()
142 MCOperand Op; in createImm()
148 static MCOperand createSFPImm(uint32_t Val) { in createSFPImm()
149 MCOperand Op; in createSFPImm()
155 static MCOperand createDFPImm(uint64_t Val) { in createDFPImm()
156 MCOperand Op; in createDFPImm()
[all …]
H A DMCInstBuilder.h38 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
44 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
50 Inst.addOperand(MCOperand::createSFPImm(Val)); in addSFPImm()
56 Inst.addOperand(MCOperand::createDFPImm(Val)); in addDFPImm()
62 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
68 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
73 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h31 class MCOperand; variable
124 MCOperand createRegOperand(unsigned int RegId) const;
125 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
126 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
127 MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;
129 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
240 static MCOperand decodeIntImmed(unsigned Imm);
241 static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm,
244 MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
245 MCOperand decodeLiteralConstant(bool ExtendFP64) const;
[all …]
H A DAMDGPUDisassembler.cpp86 addOperand(MCInst &Inst, const MCOperand& Opnd) { in addOperand()
93 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, in insertNamedMCOperand()
116 return addOperand(Inst, MCOperand::createImm(Imm)); in decodeSOPPBrTarget()
130 return addOperand(Inst, MCOperand::createImm(Offset)); in decodeSMEMOffset()
381 const MCOperand &Op = Inst.getOperand(OpIdx); in IsAGPROperand()
633 insertNamedMCOperand(MI, MCOperand::createImm(0), in getInstruction()
640 insertNamedMCOperand(MI, MCOperand::createImm(0), in getInstruction()
646 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); in getInstruction()
658 insertNamedMCOperand(MI, MCOperand::createImm(CPol), in getInstruction()
675 MI.insert(TFEIter, MCOperand::createImm(0)); in getInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp77 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR8RegisterClass()
88 Inst.addOperand(MCOperand::createReg(Register)); in DecodeLD8RegisterClass()
148 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOARr()
164 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIORdA()
172 Inst.addOperand(MCOperand::createImm(addr)); in decodeFIOBIT()
173 Inst.addOperand(MCOperand::createImm(b)); in decodeFIOBIT()
182 Inst.addOperand(MCOperand::createImm(Field << 1)); in decodeCallTarget()
199 Inst.addOperand(MCOperand::createReg(AVR::R31R30)); in decodeFLPMX()
243 Inst.addOperand(MCOperand::createImm(k)); in decodeFWRdK()
271 MCOperand::createReg((Insn & 0x40) ? AVR::R29R28 : AVR::R31R30)); in decodeMemri()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp182 MCStreamer &OutStreamer, const MCOperand &Imm, in smallData()
256 MCOperand &ImmOp = Inst.getOperand(i); in ScaleVectorOffset()
261 T.addOperand(MCOperand::createExpr(NewHE)); in ScaleVectorOffset()
280 MCOperand Reg = Inst.getOperand(0); in HexagonProcessInstruction()
281 MCOperand S16 = Inst.getOperand(1); in HexagonProcessInstruction()
286 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
294 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
301 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
308 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
315 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/Disassembler/
H A DXtensaDisassembler.cpp74 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeARRegisterClass()
89 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeSRRegisterClass()
109 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Imm << 2))); in decodeCallOperand()
116 Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm))); in decodeJumpOperand()
130 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm))); in decodeBranchOperand()
136 Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm))); in decodeBranchOperand()
145 Inst.addOperand(MCOperand::createImm( in decodeL32ROperand()
153 Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm))); in decodeImm8Operand()
161 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 8))); in decodeImm8_sh8Operand()
168 Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm))); in decodeImm12Operand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp464 Inst.addOperand(MCOperand::createReg(RRegs[getRegNum()])); in addRegGPRCOperands()
469 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getRegNum()])); in addRegGPRCNoR0Operands()
474 Inst.addOperand(MCOperand::createReg(XRegs[getRegNum()])); in addRegG8RCOperands()
479 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getRegNum()])); in addRegG8RCNoX0Operands()
484 Inst.addOperand(MCOperand::createReg(XRegs[getG8pReg()])); in addRegG8pRCOperands()
503 Inst.addOperand(MCOperand::createReg(FRegs[getRegNum()])); in addRegF4RCOperands()
508 Inst.addOperand(MCOperand::createReg(FRegs[getRegNum()])); in addRegF8RCOperands()
513 Inst.addOperand(MCOperand::createReg(FpRegs[getFpReg()])); in addRegFpRCOperands()
518 Inst.addOperand(MCOperand::createReg(VFRegs[getRegNum()])); in addRegVFRCOperands()
523 Inst.addOperand(MCOperand::createReg(VRegs[getRegNum()])); in addRegVRRCOperands()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp114 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRRegisterClass()
124 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodeFPR32RegisterClass()
134 Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo])); in DecodesFPR32RegisterClass()
144 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodesFPR64RegisterClass()
154 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodesFPR64_VRegisterClass()
164 Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo])); in DecodeFPR64RegisterClass()
176 Inst.addOperand(MCOperand::createReg(FPR128DecoderTable[RegNo])); in DecodesFPR128RegisterClass()
186 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodesGPRRegisterClass()
196 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodemGPRRegisterClass()
208 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo])); in DecodeGPRSPRegisterClass()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp87 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
319 const MCOperand &MO = MI.getOperand(Op); in getModImmOpValue()
338 const MCOperand &MO = MI.getOperand(Op); in getT2SOImmOpValue()
542 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in VFPThumb2PostEncoder()
576 llvm_unreachable("Unable to encode MCOperand!"); in getMachineOpValue()
584 const MCOperand &MO = MI.getOperand(OpIdx); in getMachineOpValue()
585 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getMachineOpValue()
614 const MCOperand &MO = MI.getOperand(OpIdx); in EncodeAddrModeOpValues()
651 const MCOperand MO = MI.getOperand(OpIdx); in encodeThumbBLOffset()
664 const MCOperand M in getThumbBLTargetOpValue()
[all...]
H A DARMInstPrinter.cpp95 const MCOperand &Reg = MI->getOperand(0); in printInst()
103 const MCOperand &Reg = MI->getOperand(0); in printInst()
111 const MCOperand &Reg = MI->getOperand(0); in printInst()
119 const MCOperand &Reg = MI->getOperand(0); in printInst()
129 const MCOperand &Dst = MI->getOperand(0); in printInst()
130 const MCOperand &MO1 = MI->getOperand(1); in printInst()
131 const MCOperand &MO2 = MI->getOperand(2); in printInst()
132 const MCOperand &MO3 = MI->getOperand(3); in printInst()
152 const MCOperand &Dst = MI->getOperand(0); in printInst()
153 const MCOperand &MO1 = MI->getOperand(1); in printInst()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp385 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
390 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands()
399 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
409 Inst.addOperand(MCOperand::createExpr(NewExpr)); in addSignedImmOperands()
544 for (MCOperand &I : MCI) in canonicalizeImmediates()
547 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in canonicalizeImmediates()
624 MCB.addOperand(MCOperand::createImm(0)); in MatchAndEmitInstruction()
657 MCB.addOperand(MCOperand::createInst(SubInst)); in MatchAndEmitInstruction()
1288 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, in makeCombineInst()
1289 MCOperand &MO2) { in makeCombineInst()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp152 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
165 const MCOperand &Op = MI->getOperand(OpNo); in printMemImmOperand()
179 const MCOperand &Op = MI->getOperand(OpNo); in printHi16ImmOperand()
191 const MCOperand &Op = MI->getOperand(OpNo); in printHi16AndImmOperand()
203 const MCOperand &Op = MI->getOperand(OpNo); in printLo16AndImmOperand()
214 const MCOperand &RegOp) { in printMemoryBaseRegister()
227 const MCOperand &OffsetOp, in printMemoryImmediateOffset()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand()
241 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); in printMemRiOperand()
242 const MCOperand &AluOp = MI->getOperand(OpNo + 2); in printMemRiOperand()
[all …]
H A DLanaiMCCodeEmitter.cpp58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
111 const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue()
138 const MCOperand AluOp = Inst.getOperand(3); in adjustPqBits()
143 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits()
189 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRiMemoryOpValue()
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue()
191 const MCOperand AluOp = Inst.getOperand(OpNo + 2); in getRiMemoryOpValue()
221 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRrMemoryOpValue()
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRrMemoryOpValue()
223 const MCOperand AluMCO in getRrMemoryOpValue()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreMCInstLower.cpp31 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
67 return MCOperand::createExpr(MCSym); in LowerSymbolOperand()
74 return MCOperand::createExpr(Add); in LowerSymbolOperand()
77 MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO, in LowerOperand()
86 return MCOperand::createReg(MO.getReg()); in LowerOperand()
88 return MCOperand::createImm(MO.getImm() + offset); in LowerOperand()
100 return MCOperand(); in LowerOperand()
107 MCOperand MCOp = LowerOperand(MO); in Lower()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVMCInstLower.cpp31 MCOperand MCOp; in lower()
44 MCOp = MCOperand::createReg(FuncReg); in lower()
48 MCOp = MCOperand::createReg(MAI->getOrCreateMBBRegister(*MO.getMBB())); in lower()
52 MCOp = MCOperand::createReg(NewReg.isValid() ? NewReg : MO.getReg()); in lower()
58 MCOp = MCOperand::createReg(Reg); in lower()
60 MCOp = MCOperand::createImm(MO.getImm()); in lower()
64 MCOp = MCOperand::createDFPImm( in lower()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MCInstLower.h20 class MCOperand;
35 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
38 MCOperand lowerSymbolOperandMachO(const MachineOperand &MO,
40 MCOperand lowerSymbolOperandELF(const MachineOperand &MO,
42 MCOperand lowerSymbolOperandCOFF(const MachineOperand &MO,
44 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
19 class MCOperand; global() variable
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp47 const MCOperand &MO = MI.getOperand(OpNo); in getDirectBrEncoding()
157 const MCOperand &MO = MI.getOperand(OpNo); in getDispRIEncoding()
170 const MCOperand &MO = MI.getOperand(OpNo); in getDispRIXEncoding()
183 const MCOperand &MO = MI.getOperand(OpNo); in getDispRIX16Encoding()
205 const MCOperand &MO = MI.getOperand(OpNo); in getDispRIHashEncoding()
218 const MCOperand &MO = MI.getOperand(OpNo); in getDispRI34PCRelEncoding()
247 const MCOperand &MO = MI.getOperand(OpNo); in getDispRI34PCRelEncoding()
261 const MCOperand &MO = MI.getOperand(OpNo); in getDispRI34PCRelEncoding()
275 const MCOperand &MO = MI.getOperand(OpNo); in getDispRI34PCRelEncoding()
294 const MCOperand in getDispRI34Encoding()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/Disassembler/
H A DLoongArchDisassembler.cpp63 Inst.addOperand(MCOperand::createReg(LoongArch::R0 + RegNo)); in DecodeGPRRegisterClass()
72 Inst.addOperand(MCOperand::createReg(LoongArch::F0 + RegNo)); in DecodeFPR32RegisterClass()
81 Inst.addOperand(MCOperand::createReg(LoongArch::F0_64 + RegNo)); in DecodeFPR64RegisterClass()
90 Inst.addOperand(MCOperand::createReg(LoongArch::FCC0 + RegNo)); in DecodeCFRRegisterClass()
99 Inst.addOperand(MCOperand::createReg(LoongArch::FCSR0 + RegNo)); in DecodeFCSRRegisterClass()
108 Inst.addOperand(MCOperand::createReg(LoongArch::VR0 + RegNo)); in DecodeLSX128RegisterClass()
117 Inst.addOperand(MCOperand::createReg(LoongArch::XR0 + RegNo)); in DecodeLASX256RegisterClass()
126 Inst.addOperand(MCOperand::createReg(LoongArch::SCR0 + RegNo)); in DecodeSCRRegisterClass()
135 Inst.addOperand(MCOperand::createImm(Imm + P)); in decodeUImmOperand()
146 Inst.addOperand(MCOperand::createImm(SignExtend64<N + S>(Imm << S))); in decodeSImmOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp80 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
91 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRX1X5RegisterClass()
102 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass()
113 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
124 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
135 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
146 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
177 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
188 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRPairRegisterClass()
199 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeSR07RegisterClass()
[all …]

12345678