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Searched refs:MCII (Results 1 – 25 of 105) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h48 MCInstrInfo const &MCII; variable
55 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
56 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
87 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
92 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
99 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
103 bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
109 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
117 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
121 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
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H A DHexagonMCInstrInfo.cpp39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
41 : MCII(MCII), BundleCurrent(Inst.begin() + in PacketIterator()
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()), in PacketIterator()
63 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in operator ++()
88 MCInstrInfo const &MCII, MCInst &MCB, in addConstExtender() argument
92 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI)); in addConstExtender()
96 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MC in addConstExtender()
103 bundleInstructions(MCInstrInfo const & MCII,MCInst const & MCI) bundleInstructions() argument
124 canonicalizePacketImpl(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCContext & Context,MCInst & MCB,HexagonMCChecker * Check) canonicalizePacketImpl() argument
171 canonicalizePacket(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCContext & Context,MCInst & MCB,HexagonMCChecker * Check,bool AttemptCompatibility) canonicalizePacket() argument
191 deriveExtender(MCInstrInfo const & MCII,MCInst const & Inst,MCOperand const & MO) deriveExtender() argument
235 extendIfNeeded(MCContext & Context,MCInstrInfo const & MCII,MCInst & MCB,MCInst const & MCI) extendIfNeeded() argument
241 getMemAccessSize(MCInstrInfo const & MCII,MCInst const & MCI) getMemAccessSize() argument
248 getAddrMode(MCInstrInfo const & MCII,MCInst const & MCI) getAddrMode() argument
255 getDesc(MCInstrInfo const & MCII,MCInst const & MCI) getDesc() argument
316 getExtendableOp(MCInstrInfo const & MCII,MCInst const & MCI) getExtendableOp() argument
323 getExtendableOperand(MCInstrInfo const & MCII,MCInst const & MCI) getExtendableOperand() argument
334 getExtentAlignment(MCInstrInfo const & MCII,MCInst const & MCI) getExtentAlignment() argument
340 getExtentBits(MCInstrInfo const & MCII,MCInst const & MCI) getExtentBits() argument
346 isExtentSigned(MCInstrInfo const & MCII,MCInst const & MCI) isExtentSigned() argument
353 getMaxValue(MCInstrInfo const & MCII,MCInst const & MCI) getMaxValue() argument
364 getMinValue(MCInstrInfo const & MCII,MCInst const & MCI) getMinValue() argument
374 getName(MCInstrInfo const & MCII,MCInst const & MCI) getName() argument
379 getNewValueOp(MCInstrInfo const & MCII,MCInst const & MCI) getNewValueOp() argument
385 getNewValueOperand(MCInstrInfo const & MCII,MCInst const & MCI) getNewValueOperand() argument
404 getNewValueOp2(MCInstrInfo const & MCII,MCInst const & MCI) getNewValueOp2() argument
411 getNewValueOperand2(MCInstrInfo const & MCII,MCInst const & MCI) getNewValueOperand2() argument
423 getType(MCInstrInfo const & MCII,MCInst const & MCI) getType() argument
430 getCVIResources(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCInst const & MCI) getCVIResources() argument
450 getUnits(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCInst const & MCI) getUnits() argument
461 getOtherReservedSlots(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCInst const & MCI) getOtherReservedSlots() argument
484 hasDuplex(MCInstrInfo const & MCII,MCInst const & MCI) hasDuplex() argument
513 hasNewValue(MCInstrInfo const & MCII,MCInst const & MCI) hasNewValue() argument
520 hasNewValue2(MCInstrInfo const & MCII,MCInst const & MCI) hasNewValue2() argument
533 isAccumulator(MCInstrInfo const & MCII,MCInst const & MCI) isAccumulator() argument
545 isConstExtended(MCInstrInfo const & MCII,MCInst const & MCI) isConstExtended() argument
587 isCanon(MCInstrInfo const & MCII,MCInst const & MCI) isCanon() argument
592 isCofMax1(MCInstrInfo const & MCII,MCInst const & MCI) isCofMax1() argument
597 isCofRelax1(MCInstrInfo const & MCII,MCInst const & MCI) isCofRelax1() argument
603 isCofRelax2(MCInstrInfo const & MCII,MCInst const & MCI) isCofRelax2() argument
609 isCompound(MCInstrInfo const & MCII,MCInst const & MCI) isCompound() argument
614 isCVINew(MCInstrInfo const & MCII,MCInst const & MCI) isCVINew() argument
624 isDuplex(MCInstrInfo const & MCII,MCInst const & MCI) isDuplex() argument
628 isExtendable(MCInstrInfo const & MCII,MCInst const & MCI) isExtendable() argument
634 isExtended(MCInstrInfo const & MCII,MCInst const & MCI) isExtended() argument
640 isFloat(MCInstrInfo const & MCII,MCInst const & MCI) isFloat() argument
645 isHVX(MCInstrInfo const & MCII,MCInst const & MCI) isHVX() argument
670 isNewValue(MCInstrInfo const & MCII,MCInst const & MCI) isNewValue() argument
676 isNewValueStore(MCInstrInfo const & MCII,MCInst const & MCI) isNewValueStore() argument
683 isOpExtendable(MCInstrInfo const & MCII,MCInst const & MCI,unsigned short O) isOpExtendable() argument
733 isPredicated(MCInstrInfo const & MCII,MCInst const & MCI) isPredicated() argument
739 isPrefix(MCInstrInfo const & MCII,MCInst const & MCI) isPrefix() argument
743 isPredicateLate(MCInstrInfo const & MCII,MCInst const & MCI) isPredicateLate() argument
750 isPredicatedNew(MCInstrInfo const & MCII,MCInst const & MCI) isPredicatedNew() argument
756 isPredicatedTrue(MCInstrInfo const & MCII,MCInst const & MCI) isPredicatedTrue() argument
768 isPredRegister(MCInstrInfo const & MCII,MCInst const & Inst,unsigned I) isPredRegister() argument
777 isSoloAX(MCInstrInfo const & MCII,MCInst const & MCI) isSoloAX() argument
783 isRestrictSlot1AOK(MCInstrInfo const & MCII,MCInst const & MCI) isRestrictSlot1AOK() argument
790 isRestrictNoSlot1Store(MCInstrInfo const & MCII,MCInst const & MCI) isRestrictNoSlot1Store() argument
798 isSolo(MCInstrInfo const & MCII,MCInst const & MCI) isSolo() argument
869 isVector(MCInstrInfo const & MCII,MCInst const & MCI) isVector() argument
938 predicateInfo(MCInstrInfo const & MCII,MCInst const & MCI) predicateInfo() argument
948 prefersSlot3(MCInstrInfo const & MCII,MCInst const & MCI) prefersSlot3() argument
954 hasTmpDst(MCInstrInfo const & MCII,MCInst const & MCI) hasTmpDst() argument
969 hasHvxTmp(MCInstrInfo const & MCII,MCInst const & MCI) hasHvxTmp() argument
985 slotsConsumed(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCInst const & MCI) slotsConsumed() argument
1054 IsABranchingInst(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCInst const & I) IsABranchingInst() argument
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H A DHexagonMCChecker.cpp58 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in init()
70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && in initReg()
74 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); in initReg()
77 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in initReg()
93 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
104 const bool IgnoreTmpDst = (HexagonMCInstrInfo::hasTmpDst(MCII, MCI) || in init()
105 HexagonMCInstrInfo::hasHvxTmp(MCII, MCI)) && in init()
127 HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) in init()
169 else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && in init()
173 else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) == in init()
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H A DHexagonMCShuffler.cpp39 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) in init()
41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
44 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
59 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
66 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
72 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
104 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument
106 HexagonMCShuffler MCS(Context, ReportErrors, MCII, STI, MCB); in HexagonMCShuffle()
130 bool llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
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H A DHexagonShuffler.cpp109 HexagonCVIResource::HexagonCVIResource(MCInstrInfo const &MCII,
115 const unsigned ItinUnits = HexagonMCInstrInfo::getCVIResources(MCII, STI, *id); in HexagonCVIResource()
131 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
132 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
169 MCInstrInfo const &MCII, in HexagonShuffler()
171 : Context(Context), BundleFlags(), MCII(MCII), STI(STI), in HexagonShuffler()
184 HexagonInstr PI(MCII, STI, &ID, Extender, S); in append()
200 const unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst); in restrictSlot1AOK()
232 if (HexagonMCInstrInfo::getDesc(MCII, Ins in restrictNoSlot1Store()
110 HexagonCVIResource(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,unsigned s,MCInst const * id) HexagonCVIResource() argument
170 HexagonShuffler(MCContext & Context,bool ReportErrors,MCInstrInfo const & MCII,MCSubtargetInfo const & STI) HexagonShuffler() argument
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H A DHexagonMCShuffler.h32 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
34 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
39 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
41 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
59 MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
61 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
64 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
H A DHexagonMCCodeEmitter.cpp342 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
407 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && in encodeSingleInstruction()
410 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in encodeSingleInstruction()
419 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in encodeSingleInstruction()
461 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, in getFixupNoBits() argument
463 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); in getFixupNoBits()
464 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI); in getFixupNoBits()
475 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI); in getFixupNoBits()
477 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR) in getFixupNoBits()
583 bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, M in getExprOpValue()
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H A DHexagonAsmBackend.cpp44 std::unique_ptr <MCInstrInfo> MCII; member in __anonab472fd70111::HexagonAsmBackend
65 relaxedCnt(0), MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
538 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
541 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
542 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && in isInstRelaxable()
544 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ && in isInstRelaxable()
546 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && in isInstRelaxable()
548 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
551 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
667 *MCII, CrntHMI, in relaxInstruction()
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H A DHexagonShuffler.h87 HexagonCVIResource(MCInstrInfo const &MCII,
107 HexagonInstr(MCInstrInfo const &MCII,
110 : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; in HexagonInstr()
164 MCInstrInfo const &MCII;
195 MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
228 return (*Pred)(MCII, Inst); in HasInstWith()
108 HexagonInstr(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCInst const * id,MCInst const * Extender,unsigned s) HexagonInstr() argument
165 MCInstrInfo const &MCII; global() variable
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DCustomBehaviour.h39 const MCInstrInfo &MCII; variable
42 InstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrPostProcess() argument
43 : STI(STI), MCII(MCII) {} in InstrPostProcess()
70 const MCInstrInfo &MCII; variable
74 const MCInstrInfo &MCII) in CustomBehaviour() argument
75 : STI(STI), SrcMgr(SrcMgr), MCII(MCII) {} in CustomBehaviour()
144 const MCInstrInfo &MCII; variable
147 InstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrumentManager() argument
148 : STI(STI), MCII(MCII) {} in InstrumentManager()
175 virtual unsigned getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.h21 std::unique_ptr<const MCInstrInfo> const MCII; variable
25 MCInstrInfo const *MCII) in AArch64Disassembler() argument
26 : MCDisassembler(STI, Ctx), MCII(MCII) {} in AArch64Disassembler()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp41 const MCInstrInfo &MCII; member in __anon88b7339b0111::WebAssemblyMCCodeEmitter
53 WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in WebAssemblyMCCodeEmitter() argument
54 : MCII(MCII), Ctx{Ctx} {} in WebAssemblyMCCodeEmitter()
58 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, in createWebAssemblyMCCodeEmitter() argument
60 return new WebAssemblyMCCodeEmitter(MCII, Ctx); in createWebAssemblyMCCodeEmitter()
92 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp37 MCInstrInfo const &MCII; member in llvm::MSP430MCCodeEmitter
74 MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in MSP430MCCodeEmitter() argument
75 : Ctx(ctx), MCII(MCII) {} in MSP430MCCodeEmitter()
86 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
204 MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, in createMSP430MCCodeEmitter()
206 return new MSP430MCCodeEmitter(Ctx, MCII); in createMSP430MCCodeEmitter()
203 createMSP430MCCodeEmitter(const MCInstrInfo & MCII,MCContext & Ctx) createMSP430MCCodeEmitter() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp35 const MCInstrInfo &MCII; member in __anondc7a8f7d0111::SystemZMCCodeEmitter
39 SystemZMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in SystemZMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in SystemZMCCodeEmitter()
138 unsigned Size = MCII.get(MI.getOpcode()).getSize(); in encodeInstruction()
168 unsigned MIBitSize = MCII.get(MI.getOpcode()).getSize() * 8; in getImmOpValue()
223 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, in createSystemZMCCodeEmitter() argument
225 return new SystemZMCCodeEmitter(MCII, Ctx); in createSystemZMCCodeEmitter()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp32 const MCInstrInfo &MCII; member in __anon657995470111::SPIRVMCCodeEmitter
35 SPIRVMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {} in SPIRVMCCodeEmitter()
53 MCCodeEmitter *llvm::createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, in createSPIRVMCCodeEmitter() argument
55 return new SPIRVMCCodeEmitter(MCII); in createSPIRVMCCodeEmitter()
119 if (hasType(MI, MCII)) in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp70 const MCInstrInfo &MCII, in computeInstrLatency() argument
72 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency()
79 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
113 const MCInstrInfo &MCII, in getReciprocalThroughput() argument
115 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput()
125 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp221 const MCInstrInfo &MCII, const MCInst &MCI, in getSchedClassID() argument
224 unsigned SchedClassID = MCII.get(Opcode).getSchedClass(); in getSchedClassID()
267 << MCII.getName(Opcode) in getSchedClassID()
277 << MCII.getName(Opcode) << ", LMUL=" << LI->getData() in getSchedClassID()
280 << " with " << MCII.getName(RVV->Pseudo) << '\n'); in getSchedClassID()
281 return MCII.get(RVV->Pseudo).getSchedClass(); in getSchedClassID()
292 const MCInstrInfo &MCII) { in createRISCVInstrumentManager() argument
293 return new RISCVInstrumentManager(STI, MCII); in createRISCVInstrumentManager()
H A DRISCVCustomBehaviour.h55 RISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in RISCVInstrumentManager() argument
56 : InstrumentManager(STI, MCII) {} in RISCVInstrumentManager()
69 getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp63 const MCInstrInfo &MCII) in AMDGPUCustomBehaviour() argument
64 : CustomBehaviour(STI, SrcMgr, MCII) { in AMDGPUCustomBehaviour()
200 << MCII.getName(Opcode) << " will be completely " in computeWaitCnt()
249 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo()
325 const MCInstrDesc &MCID = MCII.get(Opcode); in isGWS()
342 const MCInstrInfo &MCII) { in createAMDGPUCustomBehaviour() argument
343 return new AMDGPUCustomBehaviour(STI, SrcMgr, MCII); in createAMDGPUCustomBehaviour()
348 const MCInstrInfo &MCII) { in createAMDGPUInstrPostProcess() argument
349 return new AMDGPUInstrPostProcess(STI, MCII); in createAMDGPUInstrPostProcess()
H A DAMDGPUCustomBehaviour.h31 AMDGPUInstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in AMDGPUInstrPostProcess() argument
32 : InstrPostProcess(STI, MCII) {} in AMDGPUInstrPostProcess()
89 const mca::SourceMgr &SrcMgr, const MCInstrInfo &MCII);
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.h38 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
65 bool isHForm(const MCInst &MI, const MCInstrInfo *MCII);
66 bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
67 bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp33 const MCInstrInfo &MCII; member in __anonede878a50111::R600MCCodeEmitter
37 : MRI(mri), MCII(mcii) {} in R600MCCodeEmitter()
81 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
83 return new R600MCCodeEmitter(MCII, *Ctx.getRegisterInfo()); in createR600MCCodeEmitter()
90 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
157 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp440 std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); in main() local
441 assert(MCII && "Unable to create instruction info!"); in main()
444 TheTarget->createMCInstrAnalysis(MCII.get())); in main()
455 Triple(TripleName), IPtempOutputAsmVariant, *MAI, *MCII, *MRI)); in main()
470 *MCII); in main()
498 TheTarget->createInstrumentManager(*STI, *MCII)); in main()
503 IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII); in main()
513 *MCII, *IM); in main()
544 Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MRI)); in main()
567 TheTarget->createInstrPostProcess(*STI, *MCII)); in main()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp45 std::unique_ptr<MCInstrInfo const> const MCII; member in __anondc8348740111::HexagonDisassembler
50 MCInstrInfo const *MCII) in HexagonDisassembler() argument
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), in HexagonDisassembler()
65 MCInstrInfo MCII = *Disassembler.MCII; in fullValue() local
67 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) in fullValue()
69 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); in fullValue()
200 HexagonMCChecker Checker(getContext(), *MCII, STI_, MI, in getInstruction()
469 if (HexagonMCInstrInfo::isNewValue(*MCII, M in getSingleInstruction()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h39 AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in AVRMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in AVRMCCodeEmitter()
105 const MCInstrInfo &MCII; variable

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