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Searched refs:MCII (Results 1 – 25 of 110) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h48 MCInstrInfo const &MCII; variable
55 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
56 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
87 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
92 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
99 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
103 bool IsABranchingInst(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
109 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
117 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
121 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
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H A DHexagonMCInstrInfo.cpp39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
41 : MCII(MCII), BundleCurrent(Inst.begin() + in PacketIterator()
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()), in PacketIterator()
63 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in operator ++()
88 MCInstrInfo const &MCII, MCInst &MCB, in addConstExtender() argument
92 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI)); in addConstExtender()
96 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp)); in addConstExtender()
103 HexagonMCInstrInfo::bundleInstructions(MCInstrInfo const &MCII, in bundleInstructions() argument
106 return make_range(Hexagon::PacketIterator(MCII, MCI), in bundleInstructions()
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H A DHexagonMCChecker.cpp58 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in init()
70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && in initReg()
74 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); in initReg()
77 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in initReg()
93 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
104 const bool IgnoreTmpDst = (HexagonMCInstrInfo::hasTmpDst(MCII, MCI) || in init()
105 HexagonMCInstrInfo::hasHvxTmp(MCII, MCI)) && in init()
127 HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) in init()
169 else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && in init()
173 else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) == in init()
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H A DHexagonMCShuffler.cpp39 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) in init()
41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
44 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
59 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
66 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
72 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
104 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument
106 HexagonMCShuffler MCS(Context, ReportErrors, MCII, STI, MCB); in HexagonMCShuffle()
130 bool llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
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H A DHexagonShuffler.cpp108 HexagonCVIResource::HexagonCVIResource(MCInstrInfo const &MCII, in HexagonCVIResource() argument
114 const unsigned ItinUnits = HexagonMCInstrInfo::getCVIResources(MCII, STI, *id); in HexagonCVIResource()
130 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
131 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
168 MCInstrInfo const &MCII, in HexagonShuffler() argument
170 : Context(Context), BundleFlags(), MCII(MCII), STI(STI), in HexagonShuffler()
183 HexagonInstr PI(MCII, STI, &ID, Extender, S); in append()
199 const unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst); in restrictSlot1AOK()
231 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store()
372 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
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H A DHexagonMCShuffler.h32 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
34 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
39 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
41 : HexagonShuffler(Context, ReportErrors, MCII, STI) { in HexagonMCShuffler()
59 MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
61 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
64 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
H A DHexagonMCCodeEmitter.cpp371 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
436 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && in encodeSingleInstruction()
439 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in encodeSingleInstruction()
448 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in encodeSingleInstruction()
490 HexagonMCCodeEmitter::getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, in getFixupNoBits() argument
493 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); in getFixupNoBits()
494 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI); in getFixupNoBits()
505 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI); in getFixupNoBits()
507 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR) in getFixupNoBits()
613 bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) || in getExprOpValue()
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H A DHexagonAsmBackend.cpp44 std::unique_ptr <MCInstrInfo> MCII; member in __anonab472fd70111::HexagonAsmBackend
65 relaxedCnt(0), MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
410 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
413 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
414 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && in isInstRelaxable()
416 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ && in isInstRelaxable()
418 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && in isInstRelaxable()
420 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
423 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
536 *MCII, CrntHMI, in relaxInstruction()
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H A DHexagonShuffler.h87 HexagonCVIResource(MCInstrInfo const &MCII,
107 HexagonInstr(MCInstrInfo const &MCII,
110 : ID(id), Extender(Extender), Core(s), CVI(MCII, STI, s, id){}; in HexagonInstr()
164 MCInstrInfo const &MCII;
195 MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
228 return (*Pred)(MCII, Inst); in HasInstWith()
108 HexagonInstr(MCInstrInfo const & MCII,MCSubtargetInfo const & STI,MCInst const * id,MCInst const * Extender,unsigned s) HexagonInstr() argument
165 MCInstrInfo const &MCII; global() variable
/freebsd/contrib/llvm-project/llvm/include/llvm/MCA/
H A DCustomBehaviour.h40 const MCInstrInfo &MCII; variable
43 InstrPostProcess(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrPostProcess() argument
44 : STI(STI), MCII(MCII) {} in InstrPostProcess()
71 const MCInstrInfo &MCII; variable
75 const MCInstrInfo &MCII) in CustomBehaviour() argument
76 : STI(STI), SrcMgr(SrcMgr), MCII(MCII) {} in CustomBehaviour()
145 const MCInstrInfo &MCII; variable
148 InstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in InstrumentManager() argument
149 : STI(STI), MCII(MCII) {} in InstrumentManager()
176 virtual unsigned getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI,
/freebsd/contrib/llvm-project/llvm/include/llvm/DWARFCFIChecker/
H A DDWARFCFIFunctionFrameAnalyzer.h33 CFIFunctionFrameAnalyzer(MCContext &Context, const MCInstrInfo &MCII) in CFIFunctionFrameAnalyzer() argument
34 : CFIFunctionFrameReceiver(Context), MCII(MCII) {} in CFIFunctionFrameAnalyzer()
45 MCInstrInfo const &MCII;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.h21 std::unique_ptr<const MCInstrInfo> const MCII; variable
25 MCInstrInfo const *MCII) in AArch64Disassembler() argument
26 : MCDisassembler(STI, Ctx), MCII(MCII) {} in AArch64Disassembler()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp39 const MCInstrInfo &MCII; member in __anon88b7339b0111::WebAssemblyMCCodeEmitter
51 WebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in WebAssemblyMCCodeEmitter() argument
52 : MCII(MCII), Ctx{Ctx} {} in WebAssemblyMCCodeEmitter()
56 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, in createWebAssemblyMCCodeEmitter() argument
58 return new WebAssemblyMCCodeEmitter(MCII, Ctx); in createWebAssemblyMCCodeEmitter()
91 const MCInstrDesc &Desc = MCII.get(Opcode); in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp35 MCInstrInfo const &MCII; member in llvm::MSP430MCCodeEmitter
72 MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in MSP430MCCodeEmitter() argument
73 : Ctx(ctx), MCII(MCII) {} in MSP430MCCodeEmitter()
98 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
213 MCCodeEmitter *createMSP430MCCodeEmitter(const MCInstrInfo &MCII, in createMSP430MCCodeEmitter() argument
215 return new MSP430MCCodeEmitter(Ctx, MCII); in createMSP430MCCodeEmitter()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp35 const MCInstrInfo &MCII; member in __anondc7a8f7d0111::SystemZMCCodeEmitter
39 SystemZMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in SystemZMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in SystemZMCCodeEmitter()
143 unsigned Size = MCII.get(MI.getOpcode()).getSize(); in encodeInstruction()
173 unsigned MIBitSize = MCII.get(MI.getOpcode()).getSize() * 8; in getImmOpValue()
226 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, in createSystemZMCCodeEmitter() argument
228 return new SystemZMCCodeEmitter(MCII, Ctx); in createSystemZMCCodeEmitter()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.h38 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
65 bool isHForm(const MCInst &MI, const MCInstrInfo *MCII);
66 bool isQForm(const MCInst &MI, const MCInstrInfo *MCII);
67 bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII);
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp71 const MCInstrInfo &MCII, in computeInstrLatency() argument
75 STI, MCII, Inst, in computeInstrLatency()
84 STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in computeInstrLatency()
124 const MCInstrInfo &MCII, in getReciprocalThroughput() argument
126 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput()
136 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, &MCII, CPUID); in getReciprocalThroughput()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp32 const MCInstrInfo &MCII; member in __anonede878a50111::R600MCCodeEmitter
36 : MRI(mri), MCII(mcii) {} in R600MCCodeEmitter()
80 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
82 return new R600MCCodeEmitter(MCII, *Ctx.getRegisterInfo()); in createR600MCCodeEmitter()
89 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
156 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp64 const MCInstrInfo &MCII) in AMDGPUCustomBehaviour() argument
65 : CustomBehaviour(STI, SrcMgr, MCII) { in AMDGPUCustomBehaviour()
201 << MCII.getName(Opcode) << " will be completely " in computeWaitCnt()
250 const MCInstrDesc &MCID = MCII.get(Opcode); in generateWaitCntInfo()
326 const MCInstrDesc &MCID = MCII.get(Opcode); in isGWS()
345 const MCInstrInfo &MCII) { in createAMDGPUCustomBehaviour() argument
346 return new AMDGPUCustomBehaviour(STI, SrcMgr, MCII); in createAMDGPUCustomBehaviour()
351 const MCInstrInfo &MCII) { in createAMDGPUInstrPostProcess() argument
352 return new AMDGPUInstrPostProcess(STI, MCII); in createAMDGPUInstrPostProcess()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp235 const MCInstrInfo &MCII, const MCInst &MCI, in getSchedClassID() argument
238 unsigned SchedClassID = MCII.get(Opcode).getSchedClass(); in getSchedClassID()
318 << MCII.getName(Opcode) in getSchedClassID()
328 << MCII.getName(Opcode) << ", LMUL=" << LI->getData() in getSchedClassID()
331 << " with " << MCII.getName(*VPOpcode) << '\n'); in getSchedClassID()
332 return MCII.get(*VPOpcode).getSchedClass(); in getSchedClassID()
343 const MCInstrInfo &MCII) { in createRISCVInstrumentManager() argument
344 return new RISCVInstrumentManager(STI, MCII); in createRISCVInstrumentManager()
H A DRISCVCustomBehaviour.h55 RISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) in RISCVInstrumentManager() argument
56 : InstrumentManager(STI, MCII) {} in RISCVInstrumentManager()
69 getSchedClassID(const MCInstrInfo &MCII, const MCInst &MCI,
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.h39 AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx) in AVRMCCodeEmitter() argument
40 : MCII(MCII), Ctx(Ctx) {} in AVRMCCodeEmitter()
100 const MCInstrInfo &MCII; variable
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp457 std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo()); in main() local
458 assert(MCII && "Unable to create instruction info!"); in main()
461 TheTarget->createMCInstrAnalysis(MCII.get())); in main()
472 Triple(TripleName), IPtempOutputAsmVariant, *MAI, *MCII, *MRI)); in main()
487 *MCII); in main()
515 TheTarget->createInstrumentManager(*STI, *MCII)); in main()
520 IM = std::make_unique<mca::InstrumentManager>(*STI, *MCII); in main()
530 *MCII, *IM); in main()
561 Triple(TripleName), AssemblerDialect, *MAI, *MCII, *MRI)); in main()
584 TheTarget->createInstrPostProcess(*STI, *MCII)); in main()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp28 const MCInstrInfo &MCII; member in __anon657995470111::SPIRVMCCodeEmitter
31 SPIRVMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {} in SPIRVMCCodeEmitter()
52 MCCodeEmitter *llvm::createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, in createSPIRVMCCodeEmitter() argument
54 return new SPIRVMCCodeEmitter(MCII); in createSPIRVMCCodeEmitter()
140 if (hasType(MI, MCII)) in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h389 const MCInstrInfo &MCII,
395 const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
410 const MCInstrInfo &MCII,
434 const MCSubtargetInfo &STI, const MCInstrInfo &MCII, in computeInstrLatency() argument
453 const MCInstrDesc &Desc = MCII.get(Inst.getOpcode()); in computeInstrLatency()
465 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency()

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