Searched refs:M0Val (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 9971 SDValue M0Val; in LowerINTRINSIC_W_CHAIN() local
9972 M0Val = DAG.getNode(ISD::SRL, DL, MVT::i32, Op->getOperand(2), in LowerINTRINSIC_W_CHAIN()
9974 M0Val = SDValue( in LowerINTRINSIC_W_CHAIN()
9975 DAG.getMachineNode(AMDGPU::S_AND_B32, DL, MVT::i32, M0Val, in LowerINTRINSIC_W_CHAIN()
9978 Ops.push_back(copyToM0(DAG, Chain, DL, M0Val).getValue(0)); in LowerINTRINSIC_W_CHAIN()
10408 SDValue M0Val = copyToM0(DAG, Chain, DL, Op.getOperand(3)); in LowerINTRINSIC_VOID() local
10435 Ops.push_back(M0Val.getValue(0)); // Chain in LowerINTRINSIC_VOID()
10436 Ops.push_back(M0Val.getValue(1)); // Glue in LowerINTRINSIC_VOID()
10499 SDValue M0Val = copyToM0(DAG, Chain, DL, Op.getOperand(3)); in LowerINTRINSIC_VOID() local
10535 Ops.push_back(M0Val.getValue(0)); // Chain in LowerINTRINSIC_VOID()
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| H A D | AMDGPUInstructionSelector.cpp | 973 Register M0Val = MI.getOperand(6).getReg(); in selectInterpP1F16() local
974 if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI) || in selectInterpP1F16()
991 .addReg(M0Val); in selectInterpP1F16()
1813 Register M0Val = MI.getOperand(2).getReg(); in selectDSOrderedIntrinsic() local
1815 .addReg(M0Val); in selectDSOrderedIntrinsic()
1825 if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI)) in selectDSOrderedIntrinsic()
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