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Searched refs:Log2SEW (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td68 m.Log2SEW, TA_MA)>;
71 (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>;
149 vti.Vector, vti.Vector, vti.Log2SEW,
152 vti.Vector, vti.Vector, vti.Log2SEW,
165 vti.Vector, vti.Vector, vti.Log2SEW,
224 vti.Vector, vti.Vector, vti.Log2SEW,
228 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
239 vti.Vector, vti.Vector, vti.Log2SEW,
243 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
262 fvti.AVL, fvti.Log2SEW, TA_MA)>;
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H A DRISCVInstrInfoVVLPatterns.td877 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
881 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
894 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
908 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
912 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
927 wti.Vector, vti.Vector, vti.Log2SEW,
931 vti.Log2SEW, vti.LMul, wti.RegClass,
935 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,
939 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,
953 vti.Log2SEW, vti.LMul, vti.RegClass, wti.RegClass,
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H A DRISCVISelDAGToDAG.h212 uint16_t Log2SEW : 3; member
221 uint16_t Log2SEW : 3; member
231 uint16_t Log2SEW : 3; member
240 uint16_t Log2SEW : 3; member
250 uint16_t Log2SEW : 3; member
258 uint16_t Log2SEW : 3; member
266 uint16_t Log2SEW : 3; member
H A DRISCVInstrInfoZvk.td580 vti.AVL, vti.Log2SEW, TA_MA)>;
601 vti.AVL, vti.Log2SEW, TA_MA)>;
609 vti.AVL, vti.Log2SEW, TA_MA)>;
650 vti.AVL, vti.Log2SEW, TA_MA)>;
666 vti.AVL, vti.Log2SEW, TA_MA)>;
673 vti.AVL, vti.Log2SEW, TA_MA)>;
680 vti.AVL, vti.Log2SEW, TA_MA)>;
702 vti.Log2SEW,
727 vti.Log2SEW,
742 vti.Log2SEW,
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H A DRISCVInstrInfoVPseudos.td260 int Log2SEW = !logtwo(Sew);
391 int Log2SEW = 0;
583 bits<3> Log2SEW = S;
596 let Fields = ["Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
597 let PrimaryKey = ["Masked", "Strided", "FF", "Log2SEW", "LMUL"];
604 bits<3> Log2SEW = S;
612 let Fields = ["Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];
613 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
620 bits<3> Log2SEW = S;
633 let Fields = ["Masked", "Ordered", "Log2SEW", "LMU
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H A DRISCVVectorPeephole.cpp110 unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); in convertToVLMAX() local
112 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; in convertToVLMAX()
H A DRISCVOptWInstrs.cpp106 const unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MCID)).getImm(); in vectorPseudoHasAllNBitUsers() local
112 RISCV::getVectorLowDemandedScalarBits(MCOpcode, Log2SEW); in vectorPseudoHasAllNBitUsers()
387 int64_t Log2SEW = MI.getOperand(2).getImm(); in isSignExtendingOpW() local
388 assert(Log2SEW >= 3 && Log2SEW <= 6 && "Unexpected Log2SEW"); in isSignExtendingOpW()
389 return Log2SEW <= 5; in isSignExtendingOpW()
H A DRISCVISelDAGToDAG.cpp294 SDNode *Node, unsigned Log2SEW, const SDLoc &DL, unsigned CurOp, in addVectorLoadStoreOperands() argument
320 SDValue SEWOp = CurDAG->getTargetConstant(Log2SEW, DL, XLenVT); in addVectorLoadStoreOperands()
344 unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); in selectVLSEG() local
356 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided, in selectVLSEG()
360 RISCV::getVLSEGPseudo(NF, IsMasked, IsStrided, /*FF*/ false, Log2SEW, in selectVLSEG()
384 unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); in selectVLSEGFF() local
396 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, in selectVLSEGFF()
402 Log2SEW, static_cast<unsigned>(LMUL)); in selectVLSEGFF()
426 unsigned Log2SEW = Log2_32(VT.getScalarSizeInBits()); in selectVLXSEG() local
439 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, in selectVLXSEG()
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H A DRISCVInstrInfoXSf.td666 vti.Vector, XLenVT, type, vti.Log2SEW,
670 vti.Vector, XLenVT, type, vti.Log2SEW,
679 XLenVT, vti.Vector, type, vti.Log2SEW,
683 vti.Vector, vti.Vector, type, vti.Log2SEW,
687 vti.Vector, vti.Vector, type, vti.Log2SEW,
696 wti.Vector, vti.Vector, type, vti.Log2SEW,
700 wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW,
704 wti.Vector, wti.Vector, vti.Vector, type, vti.Log2SEW,
730 Vs2Info.Log2SEW, Vs2Info.LMul,
774 Vti.Log2SEW, Vt
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H A DRISCVInsertVSETVLI.cpp176 const unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm(); in isMaskRegOp() local
178 return Log2SEW == 0; in isMaskRegOp()
1029 unsigned Log2SEW = MI.getOperand(getSEWOpNum(MI)).getImm(); in computeInfoForInstr() local
1031 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; in computeInfoForInstr()
H A DRISCVInstrInfo.cpp2502 uint64_t Log2SEW = MI.getOperand(OpIdx).getImm(); in verifyInstruction() local
2503 if (Log2SEW > 31) { in verifyInstruction()
2507 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; in verifyInstruction()
3006 unsigned Log2SEW = MI.getOperand(OpIdx).getImm(); in createMIROperandComment()
3007 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8; in createMIROperandComment()
3886 RISCV::getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW) { in getVectorLowDemandedScalarBits()
3900 return Log2SEW; in getVectorLowDemandedScalarBits()
3909 return Log2SEW in getVectorLowDemandedScalarBits()
2999 unsigned Log2SEW = MI.getOperand(OpIdx).getImm(); createMIROperandComment() local
3879 getVectorLowDemandedScalarBits(uint16_t Opcode,unsigned Log2SEW) getVectorLowDemandedScalarBits() argument
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H A DRISCVInstrInfo.h345 unsigned Log2SEW);
H A DRISCVInstrInfoXTHead.td511 vti.Mask, wti.Log2SEW, vti.LMul,
524 vti.Mask, wti.Log2SEW, vti.LMul,
H A DRISCVISelLowering.cpp18588 unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); in emitVFROUND_NOEXCEPT_MASK()
18590 assert(Log2SEW >= 4); in emitVFROUND_NOEXCEPT_MASK()
18592 lookupMaskedIntrinsic(RISCV::VFCVT_F_X_V, LMul, 1 << Log2SEW) in emitVFROUND_NOEXCEPT_MASK()
18585 unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); emitVFROUND_NOEXCEPT_MASK() local