| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 918 return ExtLen == VecLen ? S : LoHalf(S, DAG); in buildHvxVectorReg()
1044 Words[IdxW].push_back(LoHalf(W0, DAG)); in createHvxPrefixPred()
1054 Words[IdxW].push_back(LoHalf(T, DAG)); in createHvxPrefixPred()
1375 V0 = LoHalf(VecV, DAG); in insertHvxSubvectorReg()
1422 SDValue R0 = LoHalf(V, DAG); in insertHvxSubvectorReg()
2512 SDValue T2 = LoHalf(P0, DAG); in emitHvxMulHsV60()
2522 {HiHalf(P2, DAG), LoHalf(P1, DAG), S16}, DAG); in emitHvxMulHsV60()
2527 SDValue T5 = LoHalf(P3, DAG); in emitHvxMulHsV60()
2570 {HiHalf(P1, DAG), LoHalf(P1, DAG)}, DAG); in emitHvxMulLoHiV60()
2573 getInstr(Hexagon::V6_vlsrw, dl, VecTy, {LoHalf(P in emitHvxMulLoHiV60()
[all...] |
| H A D | HexagonISelDAGToDAGHVX.cpp | 632 return OpRef(R.OpN & (Undef | Index | LoHalf)); in lo()
652 LoHalf = 0x20000000, enumerator
654 Whole = LoHalf | HiHalf,
729 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf); in print()
730 if (OpN & LoHalf) in print()
1191 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf); in materialize()
1194 unsigned Sub = (Part == OpRef::LoHalf) ? Hexagon::vsub_lo in materialize()
2802 // (LoHalf FoldedShuffle) in ppHvxShuffleOfShuffle()
|
| H A D | HexagonISelLowering.h | 455 SDValue LoHalf(SDValue V, SelectionDAG &DAG) const { in LoHalf() function
|
| H A D | HexagonISelLowering.cpp | 2698 ExtV = Off == 0 ? LoHalf(VecV, DAG) : HiHalf(VecV, DAG); in extractVector()
2769 T1 = LoHalf(T1, DAG); in extractVectorPred()
3029 W = LoHalf(W, DAG); in LowerCONCAT_VECTORS()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1961 MachineInstr *LoHalf = in computeBase() local
1967 (void)LoHalf; in computeBase()
1968 LLVM_DEBUG(dbgs() << " "; LoHalf->dump();); in computeBase()
|
| H A D | SIInstrInfo.cpp | 7804 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp() local
7824 Worklist.insert(&LoHalf); in splitScalar64BitUnaryOp()
7907 MachineInstr *LoHalf = in splitScalarSMulU64() local
7935 legalizeOperands(*LoHalf, MDT); in splitScalarSMulU64()
7986 MachineInstr *LoHalf = in splitScalarSMulPseudo() local
8002 legalizeOperands(*LoHalf, MDT); in splitScalarSMulPseudo()
8050 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp() local
8068 Worklist.insert(&LoHalf); in splitScalar64BitBinaryOp()
|
| H A D | SIISelLowering.cpp | 5095 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) in EmitInstrWithCustomInserter() local
5115 TII->legalizeOperands(*LoHalf); in EmitInstrWithCustomInserter()
7214 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
7219 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf); in lowerINSERT_VECTOR_ELT()
7233 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf }); in lowerINSERT_VECTOR_ELT()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4873 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D() local
4882 .addDef(LoHalf) in emitLDR_D()
4890 .addUse(LoHalf); in emitLDR_D()
|