Home
last modified time | relevance | path

Searched refs:Latency (Results 1 – 25 of 121) sorted by relevance

12345

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57WriteRes.td14 // Latency: #cyc
26 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
27 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
28 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
29 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
30 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
32 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
34 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
36 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
38 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA57WriteRes.td14 // Latency: #cyc
29 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
30 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
31 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
32 def A57Write_5cyc_1V_FP_Forward : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
33 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
34 def A57Write_5cyc_1W_Mul_Forward : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
35 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
36 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
38 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency
[all...]
H A DAArch64SchedKryoDetails.td16 let Latency = 3; let NumMicroOps = 2;
23 let Latency = 3; let NumMicroOps = 2;
30 let Latency = 4; let NumMicroOps = 3;
36 let Latency = 4; let NumMicroOps = 4;
42 let Latency = 3; let NumMicroOps = 4;
48 let Latency = 3; let NumMicroOps = 2;
54 let Latency = 3; let NumMicroOps = 2;
60 let Latency = 3; let NumMicroOps = 2;
66 let Latency = 3; let NumMicroOps = 2;
72 let Latency = 3; let NumMicroOps = 2;
[all …]
H A DAArch64SchedKryo.td66 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
67 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
69 { let Latency = 2; let NumMicroOps = 2; }
71 { let Latency = 2; let NumMicroOps = 2; }
73 { let Latency = 2; let NumMicroOps = 2; }
74 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
76 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
78 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
79 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
80 def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency
[all...]
H A DAArch64SchedAmpere1.td58 let Latency = 1;
63 let Latency = 1;
68 let Latency = 1;
73 let Latency = 1;
78 let Latency = 1;
83 let Latency = 1;
88 let Latency = 1;
93 let Latency = 2;
98 let Latency = 2;
103 let Latency = 2;
[all …]
H A DAArch64SchedExynosM3.td111 def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0;
113 def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
116 def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
117 def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
120 M3UnitC]> { let Latency = 1;
124 M3UnitC]> { let Latency = 2;
127 M3UnitC]> { let Latency = 2;
129 def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; }
130 def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; }
147 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency
[all...]
H A DAArch64SchedExynosM4.td136 def M4WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137 def M4WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
139 def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
142 def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
143 def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
144 def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
147 M4UnitC]> { let Latency = 2;
151 M4UnitC]> { let Latency = 3;
154 M4UnitC]> { let Latency = 2;
156 def M4WriteAF : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
[all …]
H A DAArch64SchedExynosM5.td136 def M5WriteZ0 : SchedWriteRes<[]> { let Latency = 0; }
137 def M5WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
139 def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
142 def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
143 def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
144 def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
146 def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
150 M5UnitE]> { let Latency = 2;
154 M5UnitC]> { let Latency = 3;
157 M5UnitC]> { let Latency = 2;
[all …]
H A DAArch64SchedAmpere1B.td53 let Latency = 1;
58 let Latency = 1;
63 let Latency = 1;
68 let Latency = 1;
73 let Latency = 1;
78 let Latency = 1;
83 let Latency = 1;
88 let Latency = 1;
93 let Latency = 1;
98 let Latency = 1;
[all …]
H A DAArch64SchedA64FX.td95 let Latency = 1;
99 let Latency = 2;
103 let Latency = 4;
107 let Latency = 6;
111 let Latency = 8;
115 let Latency = 9;
119 let Latency = 3;
123 let Latency = 5;
127 let Latency = 4;
131 let Latency
[all...]
H A DAArch64SchedTSV110.td60 def : WriteRes<WriteImm, [TSV110UnitALUAB]> { let Latency = 1; }
61 def : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; }
62 def : WriteRes<WriteISReg, [TSV110UnitMDU]> { let Latency = 2; }
63 def : WriteRes<WriteIEReg, [TSV110UnitMDU]> { let Latency = 2; }
64 def : WriteRes<WriteExtr, [TSV110UnitALUAB]> { let Latency = 1; }
65 def : WriteRes<WriteIS, [TSV110UnitALUAB]> { let Latency = 1; }
68 def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
70 def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
72 def : WriteRes<WriteIM32, [TSV110UnitMDU]> { let Latency = 3; }
73 def : WriteRes<WriteIM64, [TSV110UnitMDU]> { let Latency = 4; }
[all …]
H A DAArch64SchedThunderX.td52 def : WriteRes<WriteImm, [THXT8XUnitALU]> { let Latency = 1; }
53 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
54 def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; }
55 def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; }
56 def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; }
57 def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
61 let Latency = 4;
66 let Latency = 4;
72 let Latency = 12;
77 let Latency
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleE5500.td52 [5, 2, 2], // Latency = 1
57 [5, 2, 2], // Latency = 1
62 [5, 2, 2, 2], // Latency = 1
68 [6, 2, 2], // Latency = 1 or 2
74 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
80 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
85 [11], // Latency = 7, Repeat rate = 1
89 [11, 2, 2], // Latency = 7, Repeat rate = 7
94 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
100 [8, 2, 2], // Latency = 4, Repeat rate = 1
[all …]
H A DPPCScheduleE500mc.td48 [4, 1, 1], // Latency = 1
53 [4, 1, 1], // Latency = 1
58 [4, 1, 1, 1], // Latency = 1
64 [5, 1, 1], // Latency = 1 or 2
70 [17, 1, 1], // Latency=4..35, Repeat= 4..35
75 [11], // Latency = 8
79 [11, 1, 1], // Latency = 8
83 [7, 1, 1], // Latency = 4, Repeat rate = 1
88 [7, 1, 1], // Latency = 4, Repeat rate = 1
93 [7, 1, 1], // Latency = 4, Repeat rate = 1
[all …]
H A DPPCScheduleE500.td43 [4, 1, 1], // Latency = 1
48 [4, 1, 1], // Latency = 1
53 [4, 1, 1, 1], // Latency = 1
59 [5, 1, 1], // Latency = 1 or 2
65 [17, 1, 1], // Latency=4..35, Repeat= 4..35
70 [7, 1, 1], // Latency = 4, Repeat rate = 1
75 [7, 1, 1], // Latency = 4, Repeat rate = 1
80 [7, 1, 1], // Latency = 4, Repeat rate = 1
85 [4, 1, 1], // Latency = 1
90 [4, 1, 1], // Latency = 1
[all …]
H A DPPCScheduleP10.td70 let NumMicroOps = 0, Latency = 1 in {
86 let Latency = 7;
91 let Latency = 22;
96 let Latency = 24;
101 let Latency = 26;
106 let Latency = 27;
111 let Latency = 36;
116 let Latency = 2;
121 let Latency = 7;
127 let Latency
[all...]
H A DPPCScheduleP9.td139 let Latency = 1;
146 let Latency = 1;
153 let Latency = 1;
159 let Latency = 1;
164 let Latency = 1;
170 let Latency = 1;
175 let Latency = 1;
180 let Latency = 1;
185 let Latency = 1;
195 let Latency
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedAlderlakeP.td21 // Latency for microcoded instructions or instructions without latency info.
111 let Latency = Lat;
119 let Latency = !add(Lat, LoadLat);
138 let Latency = 11;
152 let Latency = 11;
214 let Latency = 3;
227 let Latency = 3;
254 let Latency = 7;
257 let Latency = 7;
260 let Latency = 8;
[all …]
H A DX86SchedSapphireRapids.td21 // Latency for microcoded instructions or instructions without latency info.
104 let Latency = Lat;
112 let Latency = !add(Lat, LoadLat);
131 let Latency = 11;
145 let Latency = 11;
221 let Latency = 3;
231 let Latency = 3;
250 let Latency = 7;
253 let Latency = 7;
256 let Latency = 8;
[all …]
H A DX86SchedSkylakeClient.td96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
132 def SKLWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
134 let Latency = !add(SKLWriteIMulH.Latency, SkylakeClientModel.LoadLatency);
169 let Latency = 2;
427 let Latency = 2;
432 let Latency = 6;
438 let Latency = 3;
442 let Latency = 2;
497 let Latency = 10;
[all …]
H A DX86SchedBroadwell.td97 let Latency = Lat;
105 let Latency = !add(Lat, LoadLat);
152 def BWWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
154 let Latency = !add(BWWriteIMulH.Latency, BroadwellModel.LoadLatency);
186 let Latency = 2;
492 let Latency = 2;
497 let Latency = 6;
502 let Latency = 2;
506 let Latency = 2;
514 let Latency = 11;
[all …]
H A DX86SchedHaswell.td102 let Latency = Lat;
110 let Latency = !add(Lat, LoadLat);
154 def HWWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
156 let Latency = !add(HWWriteIMulH.Latency, HaswellModel.LoadLatency);
188 let Latency = 2;
490 let Latency = 2;
495 let Latency = 6;
501 let Latency = 2;
505 let Latency = 2;
513 let Latency = 11;
[all …]
H A DX86SchedSkylakeServer.td96 let Latency = Lat;
104 let Latency = !add(Lat, LoadLat);
133 def SKXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
135 let Latency = !add(SKXWriteIMulH.Latency, SkylakeServerModel.LoadLatency);
170 let Latency = 2;
428 let Latency = 2;
433 let Latency = 6;
439 let Latency = 3;
443 let Latency = 2;
493 let Latency = 10;
[all …]
H A DX86SchedIceLake.td103 let Latency = Lat;
111 let Latency = !add(Lat, LoadLat);
140 def ICXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
142 let Latency = !add(ICXWriteIMulH.Latency, SkylakeServerModel.LoadLatency);
177 let Latency = 2;
433 let Latency = 2;
438 let Latency = 6;
444 let Latency = 3;
448 let Latency = 2;
498 let Latency = 10;
[all …]
H A DX86SchedSandyBridge.td92 let Latency = Lat;
100 let Latency = !add(Lat, LoadLat);
112 def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; }
143 def SBWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
145 let Latency = !add(SBWriteIMulH.Latency, SandyBridgeModel.LoadLatency);
181 let Latency = 2;
454 let Latency = 2;
458 let Latency = 7;
463 let Latency
[all...]

12345