Lines Matching refs:Latency
60 def : WriteRes<WriteImm, [TSV110UnitALUAB]> { let Latency = 1; }
61 def : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; }
62 def : WriteRes<WriteISReg, [TSV110UnitMDU]> { let Latency = 2; }
63 def : WriteRes<WriteIEReg, [TSV110UnitMDU]> { let Latency = 2; }
64 def : WriteRes<WriteExtr, [TSV110UnitALUAB]> { let Latency = 1; }
65 def : WriteRes<WriteIS, [TSV110UnitALUAB]> { let Latency = 1; }
68 def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
70 def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
72 def : WriteRes<WriteIM32, [TSV110UnitMDU]> { let Latency = 3; }
73 def : WriteRes<WriteIM64, [TSV110UnitMDU]> { let Latency = 4; }
76 def : WriteRes<WriteLD, [TSV110UnitLd]> { let Latency = 4; }
77 def : WriteRes<WriteLDIdx, [TSV110UnitLd]> { let Latency = 4; }
78 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
81 def : WriteRes<WriteAdr, [TSV110UnitALUAB]> { let Latency = 1; }
84 def : WriteRes<WriteST, [TSV110UnitLd0St]> { let Latency = 1; }
85 def : WriteRes<WriteSTP, [TSV110UnitLd0St]> { let Latency = 1; }
86 def : WriteRes<WriteSTIdx, [TSV110UnitLd0St]> { let Latency = 1; }
89 def : WriteRes<WriteF, [TSV110UnitF]> { let Latency = 2; }
90 def : WriteRes<WriteFCmp, [TSV110UnitF]> { let Latency = 3; }
91 def : WriteRes<WriteFCvt, [TSV110UnitF]> { let Latency = 3; }
92 def : WriteRes<WriteFCopy, [TSV110UnitF]> { let Latency = 2; }
93 def : WriteRes<WriteFImm, [TSV110UnitF]> { let Latency = 2; }
94 def : WriteRes<WriteFMul, [TSV110UnitF]> { let Latency = 5; }
97 def : WriteRes<WriteFDiv, [TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }
99 def : WriteRes<WriteVd, [TSV110UnitF]> { let Latency = 4; }
100 def : WriteRes<WriteVq, [TSV110UnitF]> { let Latency = 4; }
101 def : WriteRes<WriteVST, [TSV110UnitF]> { let Latency = 1; }
104 def : WriteRes<WriteBr, [TSV110UnitAB]> { let Latency = 1; }
105 def : WriteRes<WriteBrReg, [TSV110UnitAB]> { let Latency = 1; }
106 def : WriteRes<WriteSys, []> { let Latency = 1; }
107 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
108 def : WriteRes<WriteHint, []> { let Latency = 1; }
134 // Latency: #cyc
144 def TSV110Wr_1cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 1; }
145 def TSV110Wr_1cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 1; }
146 def TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; }
147 def TSV110Wr_1cyc_1LdSt : SchedWriteRes<[TSV110UnitLd0St]> { let Latency = 1; }
149 def TSV110Wr_2cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 2; let ReleaseAtCycles …
150 def TSV110Wr_2cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 2; }
151 def TSV110Wr_2cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 2; }
152 def TSV110Wr_2cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 2; }
153 def TSV110Wr_2cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 2; }
155 def TSV110Wr_3cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 3; }
156 def TSV110Wr_3cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 3; }
157 def TSV110Wr_3cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 3; }
159 def TSV110Wr_4cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 4; }
160 def TSV110Wr_4cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 4; }
161 def TSV110Wr_4cyc_1LdSt : SchedWriteRes<[TSV110UnitLd]> { let Latency = 4; }
162 def TSV110Wr_4cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 4; }
164 def TSV110Wr_5cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 5; }
165 def TSV110Wr_5cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 5; }
166 def TSV110Wr_5cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 5; }
167 def TSV110Wr_5cyc_1LdSt : SchedWriteRes<[TSV110UnitLd]> { let Latency = 5; }
169 def TSV110Wr_6cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 6; }
171 def TSV110Wr_7cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 7; }
173 def TSV110Wr_8cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 8; }
175 def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 11; let ReleaseAtCycles…
177 def TSV110Wr_12cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 12; let ReleaseAtCycles…
179 def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 17; let ReleaseAtCycles…
181 def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles…
183 def TSV110Wr_20cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 20; let ReleaseAtCycles…
185 def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 24; let ReleaseAtCycles…
187 def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 31; let ReleaseAtCycles…
189 def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 36; let ReleaseAtCycles…
191 def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 38; let ReleaseAtCycles…
193 def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 64; let ReleaseAtCycles…
200 let Latency = 1;
206 let Latency = 2;
212 let Latency = 2;
218 let Latency = 2;
224 let Latency = 2;
230 let Latency = 4;
236 let Latency = 4;
242 let Latency = 4;
248 let Latency = 5;
254 let Latency = 6;
260 let Latency = 6;
266 let Latency = 7;
272 let Latency = 8;
279 let Latency = 8;
288 let Latency = 6;
294 let Latency = 6;
300 let Latency = 7;
309 let Latency = 8;
315 let Latency = 8;
324 let Latency = 8;
335 let Latency = 10;