Searched refs:LaneMaskRegAttrs (Results 1 – 3 of 3) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SILowerI1Copies.cpp | 36 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs); 308 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs, in addLoopEntries() argument 318 Dom, insertUndefLaneMask(Dom, &MRI, LaneMaskRegAttrs)); 325 Pred, insertUndefLaneMask(Pred, &MRI, LaneMaskRegAttrs)); 417 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs) { in createLaneMaskReg() argument 418 return MRI->createVirtualRegister(LaneMaskRegAttrs); in createLaneMaskReg() 423 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs) { in insertUndefLaneMask() argument 427 Register UndefReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in insertUndefLaneMask() 599 LF.addLoopEntries(FoundLoopLevel, SSAUpdater, *MRI, LaneMaskRegAttrs, in lowerPhis() 603 Incoming.UpdatedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in lowerPhis() [all …]
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H A D | SILowerI1Copies.h | 35 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs); 51 MachineRegisterInfo::VRegAttrs LaneMaskRegAttrs; variable 72 LaneMaskRegAttrs = MRI->getVRegAttrs(LaneMask); in initializeLaneMaskRegisterAttributes()
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H A D | AMDGPUGlobalISelDivergenceLowering.cpp | 132 Register LaneMask = createLaneMaskReg(MRI, LaneMaskRegAttrs); in buildRegCopyToLaneMask() 171 Register PrevMaskedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in buildMergeLaneMasks() 172 Register CurMaskedReg = createLaneMaskReg(MRI, LaneMaskRegAttrs); in buildMergeLaneMasks()
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