Home
last modified time | relevance | path

Searched refs:LO16 (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp61 uint16_t LO16 = static_cast<uint16_t>(Bin); writeData() local
235 uint16_t LO16 = static_cast<uint16_t>(Bin); encodeInstruction() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp1070 MachineInstrBuilder LO16, HI16; in ExpandMOV32BitImm() local
1083 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
1090 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); in ExpandMOV32BitImm()
1100 LO16 = LO16.addImm(SOImmValV1); in ExpandMOV32BitImm()
1102 LO16.cloneMemRefs(MI); in ExpandMOV32BitImm()
1104 LO16.setMIFlags(MIFlags); in ExpandMOV32BitImm()
1106 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp()); in ExpandMOV32BitImm()
1109 LO16.add(makeImplicit(MI.getOperand(1))); in ExpandMOV32BitImm()
1110 LO16.copyImplicitOps(MI); in ExpandMOV32BitImm()
1127 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); in ExpandMOV32BitImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td64 def LO16 : SDNodeXForm<imm, [{
122 return ((N->getZExtValue() & 0xFFFFUL) == N->getZExtValue());}], LO16> {
129 return (Imm < 0) && (isInt<16>(Imm));}], LO16> {
135 return ((int64_t)(N->getSExtValue() & 0xFFFFUL) == N->getSExtValue());}], LO16> {
143 return (N->getZExtValue() >= 0xFFFF0000UL);}], LO16> {
835 def : Pat<(i32 imm:$imm), (OR_I_LO (MOVHI (HI16 imm:$imm)), (LO16 imm:$imm))>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.td492 def LO16 : SDNodeXForm<imm, [{
543 }], LO16>;
3117 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
3127 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
3130 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
3133 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
3796 (LO16 imm:$imm)), sub_eq)>;
3836 (LO16 imm:$imm)), sub_eq)>;
3866 (LO16 imm:$imm)), sub_eq)>;
3895 (LO16 imm:$imm)), sub_eq)>;
H A DPPCInstrP10.td2032 (LO16 imm:$imm)), sub_eq)>;
2039 (LO16 imm:$imm)), sub_eq)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td1192 def LO16 : SDNodeXForm<imm, [{
1221 // The LO16 param means that only the lower 16 bits of the node
1229 }], LO16>;
1282 }], LO16>;
3129 (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>;
H A DMips64InstrInfo.td653 (LO16 imm:$imm))>, ISA_MIPS3, GPR_64;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td602 // This is the base class for VGPR{128..255}_{LO16,HI16}.
616 // This is the base class for VGPR{0..127}_{LO16,HI16}.