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Searched refs:LMul (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp203 unsigned LMul; in printVType() local
205 std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType)); in printVType()
211 OS << LMul; in printVType()
225 unsigned LMul; in getSEWLMULRatio() local
227 std::tie(LMul, Fractional) = decodeVLMUL(VLMul); in getSEWLMULRatio()
230 LMul = Fractional ? (8 / LMul) : (LMul * 8); in getSEWLMULRatio()
233 return (SEW * 8) / LMul; in getSEWLMULRatio()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td133 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
136 vti.LMul, vti.AVL, vti.RegClass,
149 vti.LMul, vti.AVL, vti.RegClass,
208 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
211 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
223 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
226 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
240 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW,
241 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX))
256 instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW,
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H A DRISCVInstrInfoZvk.td213 …vs2_types = !cond(!eq(vd_lmul, "M8") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 32)),
214 … !eq(vd_lmul, "M4") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 32)),
215 … !eq(vd_lmul, "M2") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 16)),
216 … !eq(vd_lmul, "M1") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 8)),
217 … !eq(vd_lmul, "MF2") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 4)),
218 … !eq(vd_lmul, "MF4") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 2)),
219 … !eq(vd_lmul, "MF8") : !filter(vti, I32IntegerVectors, !le(vti.LMul.octuple, 1)));
594 (!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX)
617 (!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX)
625 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)
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H A DRISCVInstrInfoVVLPatterns.td949 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
953 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
966 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
980 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
984 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
1000 vti.LMul, wti.RegClass, vti.RegClass>;
1003 vti.Log2SEW, vti.LMul, wti.RegClass,
1007 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,
1011 vti.Log2SEW, vti.LMul, wti.RegClass, wti.RegClass,
1079 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
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H A DRISCVInstrInfoVPseudos.td292 LMULInfo LMul = M;
415 LMULInfo LMul = M;
1892 defvar mx = mti.LMul.MX;
1894 let VLMul = mti.LMul.value in {
1968 defvar mx = mti.LMul.MX;
1970 let VLMul = mti.LMul.value in {
2024 defvar mx = mti.LMul.MX;
2025 let VLMul = mti.LMul.value in {
2037 defvar mx = mti.LMul.MX;
2038 let VLMul = mti.LMul.value in {
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H A DRISCVInstrInfoXRivos.td102 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
177 (!cast<Instruction>("PseudoRI_VEXTRACT_" # vti.LMul.MX)
185 (!cast<Instruction>("PseudoRI_VINSERT_" # vti.LMul.MX)
H A DRISCVInstrInfoXSf.td686 "PseudoSF_VC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
690 "PseudoSF_VC_V_" # instruction_suffix # "_" # vti.LMul.MX,
699 "PseudoSF_VC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
703 "PseudoSF_VC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
707 "PseudoSF_VC_V_" # instruction_suffix # "_" # vti.LMul.MX,
716 "PseudoSF_VC_" # instruction_suffix # "_SE_" # vti.LMul.MX,
720 "PseudoSF_VC_V_" # instruction_suffix # "_SE_" # vti.LMul.MX,
724 "PseudoSF_VC_V_" # instruction_suffix # "_" # vti.LMul.MX,
751 Vs2Info.Log2SEW, Vs2Info.LMul,
793 "Pseudo" # instruction # "_" # Vti.LMul.MX,
H A DRISCVInsertVSETVLI.cpp272 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL); in isLMUL1OrSmaller()
273 return Fractional || LMul == 1; in isLMUL1OrSmaller()
811 unsigned LMul; in print() local
813 std::tie(LMul, Fractional) = decodeVLMUL(VLMul); in print()
820 OS << LMul << ", " in print()
967 auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMul); in computeVLMAX()
969 VLEN = VLEN / LMul; in computeVLMAX()
971 VLEN = VLEN * LMul; in computeVLMAX()
H A DRISCVSchedSiFiveP400.td95 defvar LMul = SiFiveP400GetLMulCycles<mx>.c;
96 int latency = !mul(LMul, 2);
442 foreach LMul = [1, 2, 4, 8] in {
443 let Latency = 8, ReleaseAtCycles = [LMul] in {
444 def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP400VLD]>;
445 def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP400VST]>;
447 let Latency = 2, ReleaseAtCycles = [LMul] in {
448 def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP400VEXQ0]>;
H A DRISCVInstrInfoXAndes.td515 fvti.Log2SEW, fvti.LMul,
527 fvti.Log2SEW, fvti.LMul,
565 instruction#"_"#kind#"_"#vti.LMul.MX,
588 wti.Mask, wti.Log2SEW, vti.LMul,
H A DRISCVSchedSiFiveP800.td406 foreach LMul = [1, 2, 4, 8] in {
407 let Latency = 8, ReleaseAtCycles = [LMul] in {
408 def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP800VLD]>;
409 def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP800VST]>;
411 let Latency = 2, ReleaseAtCycles = [LMul] in {
412 def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP800VectorArith]>;
H A DRISCVSchedSiFiveP600.td618 foreach LMul = [1, 2, 4, 8] in {
619 let Latency = 8, ReleaseAtCycles = [LMul] in {
620 def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP600VLD]>;
621 def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP600VST]>;
623 let Latency = 2, ReleaseAtCycles = [LMul] in {
624 def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP600VectorArith]>;
H A DRISCVInstrInfo.cpp259 RISCVVType::VLMUL LMul) { in isConvertibleToVMV_V_V() argument
291 if (FirstLMul != LMul) in isConvertibleToVMV_V_V()
319 return LMul == RISCVVType::getVLMUL(VType); in isConvertibleToVMV_V_V()
386 RISCVVType::VLMUL LMul = RISCVRI::getLMul(RegClass->TSFlags); in copyPhysRegVector() local
391 auto [LMulVal, Fractional] = RISCVVType::decodeVLMUL(LMul); in copyPhysRegVector()
464 if (LMul == LMulCopied && in copyPhysRegVector()
465 isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) { in copyPhysRegVector()
H A DRISCVInstrInfoXTHead.td528 vti.Mask, wti.Log2SEW, vti.LMul,
541 vti.Mask, wti.Log2SEW, vti.LMul,
H A DRISCVISelLowering.h375 static unsigned getRegClassIDForLMUL(RISCVVType::VLMUL LMul);
H A DRISCVISelLowering.cpp2562 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVVType::VLMUL LMul) { in getRegClassIDForLMUL() argument
2563 switch (LMul) { in getRegClassIDForLMUL()
2805 unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen); in useRVVForFixedLengthVectorVT() local
2807 if (LMul > Subtarget.getMaxLMULForFixedLengthVectors()) in useRVVForFixedLengthVectorVT()
2986 unsigned LMul; in getLMULCost() local
2988 std::tie(LMul, Fractional) = in getLMULCost()
2991 Cost = LMul <= DLenFactor ? (DLenFactor / LMul) : 1; in getLMULCost()
2993 Cost = (LMul * DLenFactor); in getLMULCost()
10494 SDValue LMul = DAG.getTargetConstant(VLMUL, DL, XLenVT); in lowerGetVectorLength() local
10501 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, ID, AVL, Sew, LMul); in lowerGetVectorLength()
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