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Searched refs:ItinData (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp33 : DebugType(ParentDebugType), ItinData(II), DAG(SchedDAG) { in ScoreboardHazardRecognizer()
39 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
41 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer()
44 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
45 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
73 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
113 if (!ItinData || ItinData->isEmpty()) in getHazardType()
128 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
129 *E = ItinData->endStage(idx); IS != E; ++IS) { in getHazardType()
172 if (!ItinData || ItinData->isEmpty()) in EmitInstruction()
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H A DTargetInstrInfo.cpp1753 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
1756 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
1764 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1766 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1769 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1771 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1777 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1784 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
1786 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1790 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h318 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
321 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
326 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
422 std::optional<unsigned> getVLDMDefCycle(const InstrItineraryData *ItinData,
426 std::optional<unsigned> getLDMDefCycle(const InstrItineraryData *ItinData,
430 std::optional<unsigned> getVSTMUseCycle(const InstrItineraryData *ItinData,
434 std::optional<unsigned> getSTMUseCycle(const InstrItineraryData *ItinData,
438 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
446 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
453 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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H A DARMBaseInstrInfo.cpp3304 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, in getNumMicroOpsSwiftLdSt() argument
3309 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3606 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
3608 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
3613 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
3616 return getNumMicroOpsSwiftLdSt(ItinData, MI); in getNumMicroOps()
3720 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle() argument
3726 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3760 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle() argument
3766 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h34 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer() argument
36 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), in PPCDispatchGroupSBHazardRecognizer()
H A DPPCInstrInfo.h443 unsigned getInstrLatency(const InstrItineraryData *ItinData,
447 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
452 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
456 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
H A DPPCInstrInfo.cpp136 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
139 if (!ItinData || UseOldLatencyCalc) in getInstrLatency()
140 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency()
156 std::optional<unsigned> Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency()
167 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency() argument
170 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency()
191 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp82 const Record *ItinData, std::string &ItinString,
84 void formItineraryOperandCycleString(const Record *ItinData,
88 const Record *ItinData,
342 const Record *ItinData, in formItineraryStageString() argument
346 ConstRecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in formItineraryStageString()
388 const Record *ItinData, std::string &ItinString, unsigned &NOperandCycles) { in formItineraryOperandCycleString() argument
391 ItinData->getValueAsListOfInts("OperandCycles"); in formItineraryOperandCycleString()
404 const Record *ItinData, in formItineraryBypassString() argument
407 ConstRecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in formItineraryBypassString()
501 const Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in emitStageAndOperandCycleData() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h280 unsigned getInstrLatency(const InstrItineraryData *ItinData,
313 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
461 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
H A DHexagonInstrInfo.cpp1973 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1976 return getInstrTimingClassLatency(ItinData, MI); in getInstrLatency()
4312 const InstrItineraryData *ItinData, const MachineInstr &MI) const { in getInstrTimingClassLatency() argument
4315 if (!ItinData) in getInstrTimingClassLatency()
4316 return getInstrLatency(ItinData, MI); in getInstrTimingClassLatency()
4320 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrTimingClassLatency()
4332 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency() argument
4363 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScoreboardHazardRecognizer.h95 const InstrItineraryData *ItinData; variable
H A DTargetInstrInfo.h1833 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1845 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode,
1857 getOperandLatency(const InstrItineraryData *ItinData,
1864 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1870 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h209 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
H A DR600InstrInfo.cpp971 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
H A DSIInstrInfo.h1487 unsigned getInstrLatency(const InstrItineraryData *ItinData,
H A DSIInstrInfo.cpp10001 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.cpp1122 for (const Record *ItinData : ItinRecords) { in collectProcItins() local
1123 const Record *ItinDef = ItinData->getValueAsDef("TheClass"); in collectProcItins()
1129 ProcModel.ItinDefList[SC.Index] = ItinData; in collectProcItins()