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Searched refs:ItinData (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp33 : DebugType(ParentDebugType), ItinData(II), DAG(SchedDAG) { in ScoreboardHazardRecognizer()
39 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer()
41 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer()
44 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
45 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
73 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
113 if (!ItinData || ItinData->isEmpty()) in getHazardType()
128 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
129 *E = ItinData->endStage(idx); IS != E; ++IS) { in getHazardType()
172 if (!ItinData || ItinData->isEmpty()) in EmitInstruction()
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H A DTargetInstrInfo.cpp1442 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
1445 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
1453 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1455 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1458 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1460 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
1466 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1473 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
1475 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
1479 int UOps = ItinData->Itineraries[Class].NumMicroOps; in getNumMicroOps()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h321 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
324 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
329 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
431 std::optional<unsigned> getVLDMDefCycle(const InstrItineraryData *ItinData,
435 std::optional<unsigned> getLDMDefCycle(const InstrItineraryData *ItinData,
439 std::optional<unsigned> getVSTMUseCycle(const InstrItineraryData *ItinData,
443 std::optional<unsigned> getSTMUseCycle(const InstrItineraryData *ItinData,
447 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
455 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
462 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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H A DARMBaseInstrInfo.cpp3461 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, in getNumMicroOpsSwiftLdSt() argument
3466 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3763 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
3765 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
3770 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
3773 return getNumMicroOpsSwiftLdSt(ItinData, MI); in getNumMicroOps()
3877 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle() argument
3883 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3917 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle() argument
3923 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h34 PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, in PPCDispatchGroupSBHazardRecognizer() argument
36 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), in PPCDispatchGroupSBHazardRecognizer()
H A DPPCInstrInfo.h333 unsigned getInstrLatency(const InstrItineraryData *ItinData,
337 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
342 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
346 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
H A DPPCInstrInfo.cpp138 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
141 if (!ItinData || UseOldLatencyCalc) in getInstrLatency()
142 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency()
158 std::optional<unsigned> Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency()
169 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency() argument
172 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency()
193 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp93 void FormItineraryStageString(const std::string &Names, Record *ItinData,
95 void FormItineraryOperandCycleString(Record *ItinData,
98 void FormItineraryBypassString(const std::string &Names, Record *ItinData,
354 Record *ItinData, in FormItineraryStageString() argument
358 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
400 Record *ItinData, std::string &ItinString, unsigned &NOperandCycles) { in FormItineraryOperandCycleString() argument
403 ItinData->getValueAsListOfInts("OperandCycles"); in FormItineraryOperandCycleString()
416 Record *ItinData, in FormItineraryBypassString() argument
419 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
516 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; in EmitStageAndOperandCycleData() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h280 unsigned getInstrLatency(const InstrItineraryData *ItinData,
312 std::optional<unsigned> getOperandLatency(const InstrItineraryData *ItinData,
460 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
H A DHexagonInstrInfo.cpp1970 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
1973 return getInstrTimingClassLatency(ItinData, MI); in getInstrLatency()
4308 const InstrItineraryData *ItinData, const MachineInstr &MI) const { in getInstrTimingClassLatency() argument
4311 if (!ItinData) in getInstrTimingClassLatency()
4312 return getInstrLatency(ItinData, MI); in getInstrTimingClassLatency()
4316 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrTimingClassLatency()
4328 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency() argument
4359 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScoreboardHazardRecognizer.h95 const InstrItineraryData *ItinData; variable
H A DTargetInstrInfo.h1758 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1770 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode,
1782 getOperandLatency(const InstrItineraryData *ItinData,
1789 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1795 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h207 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
H A DSIInstrInfo.h1423 unsigned getInstrLatency(const InstrItineraryData *ItinData,
H A DR600InstrInfo.cpp981 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
H A DSIInstrInfo.cpp9534 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.cpp1165 for (Record *ItinData : ItinRecords) { in collectProcItins()
1166 const Record *ItinDef = ItinData->getValueAsDef("TheClass"); in collectProcItins()
1173 ProcModel.ItinDefList[SC.Index] = ItinData; in collectProcItins()