| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetCallingConv.h | 29 unsigned IsZExt : 1; ///< Zero extended
63 : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsByRef(0), in ArgFlagsTy()
73 bool isZExt() const { return IsZExt; } in isZExt()
74 void setZExt() { IsZExt = 1; } in setZExt()
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| H A D | MachineFrameInfo.h | 542 void setObjectZExt(int ObjectIdx, bool IsZExt) { in setObjectZExt() argument
545 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
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| H A D | TargetLowering.h | 303 bool IsZExt : 1; variable
320 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false), in ArgListEntry()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 206 bool WantResult = true, bool IsZExt = false);
224 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
225 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
238 bool IsZExt = false);
242 bool IsZExt = false);
260 bool IsZExt = true);
263 bool IsZExt = true);
266 bool IsZExt = false);
305 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
312 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
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| H A D | AArch64ISelLowering.cpp | 4885 Entry.IsZExt = false; in LowerFSINCOS()
17669 bool IsZExt = false; in performVecReduceAddCombineWithUADDLP() local
17671 IsZExt = true; in performVecReduceAddCombineWithUADDLP()
17673 IsZExt = false; in performVecReduceAddCombineWithUADDLP()
17694 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
17705 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 161 const TargetRegisterClass *RC, bool IsZExt = true,
168 unsigned DestReg, bool IsZExt);
450 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
479 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
483 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
818 bool IsZExt, unsigned DestReg, in PPCEmitCmp() argument
843 Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() : in PPCEmitCmp()
845 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
918 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
920 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
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| H A D | PPCInstrInfo.cpp | 5261 bool IsZExt = definedByZeroExtendingOp(Reg, MRI); in isSignOrZeroExtended() local
5265 if (IsSExt && IsZExt) in isSignOrZeroExtended()
5266 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
5280 SrcExt.second || IsZExt); in isSignOrZeroExtended()
5291 IsZExt |= FuncInfo->isLiveInZExt(VReg); in isSignOrZeroExtended()
5292 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
5300 SrcExt.second || IsZExt); in isSignOrZeroExtended()
5310 std::pair<bool, bool> IsExtendPair = std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
5328 IsZExt |= Attrs.hasAttribute(Attribute::ZExt); in isSignOrZeroExtended()
5329 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
[all …]
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| H A D | PPCISelLowering.cpp | 18507 Entry.IsZExt = !Entry.IsSExt; in lowerToLibCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 186 bool IsZExt);
1751 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
1752 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1889 unsigned DestReg, bool IsZExt) { in emitIntExt() argument
1897 if (IsZExt) in emitIntExt()
1976 bool IsZExt = Opcode == Instruction::LShr; in selectShift() local
1977 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 781 bool IsZExt = (Ld->getExtensionType() == ISD::ZEXTLOAD); in tryIndexedLoad() local
784 Opcode = IsZExt ? RISCV::TH_LBUIB : RISCV::TH_LBIB; in tryIndexedLoad()
786 Opcode = IsZExt ? RISCV::TH_LBUIA : RISCV::TH_LBIA; in tryIndexedLoad()
788 Opcode = IsZExt ? RISCV::TH_LHUIB : RISCV::TH_LHIB; in tryIndexedLoad()
790 Opcode = IsZExt ? RISCV::TH_LHUIA : RISCV::TH_LHIA; in tryIndexedLoad()
792 Opcode = IsZExt ? RISCV::TH_LWUIB : RISCV::TH_LWIB; in tryIndexedLoad()
794 Opcode = IsZExt ? RISCV::TH_LWUIA : RISCV::TH_LWIA; in tryIndexedLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 1049 bool IsZExt = isa<ZExtInst>(CastOp); in foldBinOpOfSelectAndCastOfSelectCondition() local
1054 } else if (IsZExt) { in foldBinOpOfSelectAndCastOfSelectCondition()
3800 bool IsZExt = isa<ZExtInst>(Cond); in visitSwitchInst() local
3806 return IsZExt ? CaseVal.isIntN(NewWidth) in visitSwitchInst()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2127 Entry.IsZExt = !Entry.IsSExt; in ExpandLibCall()
2280 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2289 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2372 Entry.IsZExt = false; in ExpandSinCosLibCall()
2380 Entry.IsZExt = false; in ExpandSinCosLibCall()
2388 Entry.IsZExt = false; in ExpandSinCosLibCall()
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| H A D | LegalizeVectorOps.cpp | 1901 Entry.IsZExt = false; in tryExpandVecMathCall()
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| H A D | FastISel.cpp | 1042 if (Arg.IsZExt) in lowerCallTo()
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| H A D | SelectionDAGBuilder.cpp | 10851 Entry.IsZExt = false; in LowerCallTo()
10953 if (Args[i].IsZExt) in LowerCallTo()
11032 else if (Args[i].IsZExt) in LowerCallTo()
11056 CLI.RetZExt == Args[i].IsZExt)) in LowerCallTo()
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| H A D | LegalizeIntegerTypes.cpp | 5013 Entry.IsZExt = false; in ExpandIntRes_XMULO()
5021 Entry.IsZExt = false; in ExpandIntRes_XMULO()
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| H A D | TargetLowering.cpp | 115 IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); in setAttributes()
164 Entry.IsZExt = !Entry.IsSExt; in makeLibCall()
168 Entry.IsSExt = Entry.IsZExt = false; in makeLibCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 570 Entry.IsZExt = !IsSigned; in LowerDivRem()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9960 Entry.IsZExt = false; in LowerFSINCOS()
9970 Entry.IsZExt = false; in LowerFSINCOS()
20710 Entry.IsZExt = !isSigned; in getDivRemArgList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2130 Entry.IsZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), IsSigned); in makeExternalCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 21480 Entry.IsZExt = true; in LowerFP_EXTEND()
21574 Entry.IsZExt = true; in LowerFP_ROUND()
28988 Entry.IsZExt = false; in LowerWin64_i128OP()
31870 Entry.IsZExt = false; in LowerFSINCOS()
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