| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetCallingConv.h | 29 unsigned IsZExt : 1; ///< Zero extended
64 : IsZExt(0), IsSExt(0), IsNoExt(0), IsInReg(0), IsSRet(0), IsByVal(0), in ArgFlagsTy()
74 bool isZExt() const { return IsZExt; } in isZExt()
75 void setZExt() { IsZExt = 1; } in setZExt()
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| H A D | MachineFrameInfo.h | 544 void setObjectZExt(int ObjectIdx, bool IsZExt) { in setObjectZExt() argument
547 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
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| H A D | TargetLowering.h | 306 bool IsZExt : 1; variable
324 : IsSExt(false), IsZExt(false), IsNoExt(false), IsInReg(false), in ArgListEntry()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 201 bool WantResult = true, bool IsZExt = false);
218 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
219 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
232 bool IsZExt = false);
236 bool IsZExt = false);
254 bool IsZExt = true);
257 bool IsZExt = true);
260 bool IsZExt = false);
299 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
306 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
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| H A D | AArch64ISelLowering.cpp | 5083 Entry.IsZExt = false; in LowerFSINCOS()
18140 bool IsZExt = false; in performVecReduceAddCombineWithUADDLP() local
18142 IsZExt = true; in performVecReduceAddCombineWithUADDLP()
18144 IsZExt = false; in performVecReduceAddCombineWithUADDLP()
18165 SDValue UABDHigh8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
18176 SDValue UABDLo8 = DAG.getNode(IsZExt ? ISD::ABDU : ISD::ABDS, DL, MVT::v8i8, in performVecReduceAddCombineWithUADDLP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 154 const TargetRegisterClass *RC, bool IsZExt = true,
160 bool IsZExt);
438 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
467 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
471 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
806 bool IsZExt, Register DestReg, in PPCEmitCmp() argument
831 Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() : in PPCEmitCmp()
833 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
906 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
908 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
[all …]
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| H A D | PPCInstrInfo.cpp | 5500 bool IsZExt = definedByZeroExtendingOp(Reg, MRI); in isSignOrZeroExtended() local
5504 if (IsSExt && IsZExt) in isSignOrZeroExtended()
5505 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
5519 SrcExt.second || IsZExt); in isSignOrZeroExtended()
5530 IsZExt |= FuncInfo->isLiveInZExt(VReg); in isSignOrZeroExtended()
5531 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
5539 SrcExt.second || IsZExt); in isSignOrZeroExtended()
5549 std::pair<bool, bool> IsExtendPair = std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
5567 IsZExt |= Attrs.hasAttribute(Attribute::ZExt); in isSignOrZeroExtended()
5568 return std::pair<bool, bool>(IsSExt, IsZExt); in isSignOrZeroExtended()
[all …]
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| H A D | PPCISelLowering.cpp | 19509 Entry.IsZExt = !Entry.IsSExt; in lowerToLibCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 184 bool IsZExt);
1763 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
1764 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
1901 unsigned DestReg, bool IsZExt) { in emitIntExt() argument
1909 if (IsZExt) in emitIntExt()
1991 bool IsZExt = Opcode == Instruction::LShr; in selectShift() local
1992 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt)) in selectShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 539 bool IsZExt = get<0>(MatchInfo); in applyExtMulToMULL() local
545 unsigned ExtOpc = IsZExt ? TargetOpcode::G_ZEXT : TargetOpcode::G_SEXT; in applyExtMulToMULL()
552 B.buildInstr(IsZExt ? AArch64::G_UMULL : AArch64::G_SMULL, in applyExtMulToMULL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 855 bool IsZExt = (Ld->getExtensionType() == ISD::ZEXTLOAD); in tryIndexedLoad() local
858 Opcode = IsZExt ? RISCV::TH_LBUIB : RISCV::TH_LBIB; in tryIndexedLoad()
860 Opcode = IsZExt ? RISCV::TH_LBUIA : RISCV::TH_LBIA; in tryIndexedLoad()
862 Opcode = IsZExt ? RISCV::TH_LHUIB : RISCV::TH_LHIB; in tryIndexedLoad()
864 Opcode = IsZExt ? RISCV::TH_LHUIA : RISCV::TH_LHIA; in tryIndexedLoad()
866 Opcode = IsZExt ? RISCV::TH_LWUIB : RISCV::TH_LWIB; in tryIndexedLoad()
868 Opcode = IsZExt ? RISCV::TH_LWUIA : RISCV::TH_LWIA; in tryIndexedLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstructionCombining.cpp | 1077 bool IsZExt = isa<ZExtInst>(CastOp); in foldBinOpOfSelectAndCastOfSelectCondition() local
1082 } else if (IsZExt) { in foldBinOpOfSelectAndCastOfSelectCondition()
4190 bool IsZExt = isa<ZExtInst>(Cond); in visitSwitchInst() local
4196 return IsZExt ? CaseVal.isIntN(NewWidth) in visitSwitchInst()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2191 Entry.IsZExt = !Entry.IsSExt; in ExpandLibCall()
2334 Arg.IsZExt = !Arg.IsSExt; in ExpandBitCountingLibCall()
2380 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
2389 Entry.IsZExt = !isSigned; in ExpandDivRemLibCall()
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| H A D | FastISel.cpp | 1039 if (Arg.IsZExt) in lowerCallTo()
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| H A D | LegalizeVectorOps.cpp | 2229 Entry.IsZExt = false; in tryExpandVecMathCall()
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| H A D | SelectionDAGBuilder.cpp | 11012 Entry.IsZExt = false; in LowerCallTo()
11114 if (Args[i].IsZExt) in LowerCallTo()
11195 else if (Args[i].IsZExt) in LowerCallTo()
11219 CLI.RetZExt == Args[i].IsZExt)) in LowerCallTo()
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| H A D | LegalizeIntegerTypes.cpp | 5249 Entry.IsZExt = false; in ExpandIntRes_XMULO()
5257 Entry.IsZExt = false; in ExpandIntRes_XMULO()
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| H A D | TargetLowering.cpp | 122 IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt); in setAttributes()
175 Entry.IsZExt = !Entry.IsSExt; in makeLibCall()
179 Entry.IsSExt = Entry.IsZExt = false; in makeLibCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 513 Entry.IsZExt = !IsSigned; in LowerDivRem()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10011 Entry.IsZExt = false; in LowerFSINCOS()
10021 Entry.IsZExt = false; in LowerFSINCOS()
20644 Entry.IsZExt = !isSigned; in getDivRemArgList()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2468 Entry.IsZExt = !Entry.IsSExt; in makeExternalCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22210 Entry.IsZExt = true; in LowerFP_EXTEND()
22309 Entry.IsZExt = true; in LowerFP_ROUND()
30051 Entry.IsZExt = false; in LowerWin64_i128OP()
33079 Entry.IsZExt = false; in LowerFSINCOS()
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