Lines Matching refs:IsZExt
161 const TargetRegisterClass *RC, bool IsZExt = true,
168 unsigned DestReg, bool IsZExt);
450 bool IsZExt, unsigned FP64LoadOpc) { in PPCEmitLoad() argument
479 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8) in PPCEmitLoad()
483 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8) in PPCEmitLoad()
818 bool IsZExt, unsigned DestReg, in PPCEmitCmp() argument
843 Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() : in PPCEmitCmp()
845 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))) in PPCEmitCmp()
918 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW; in PPCEmitCmp()
920 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI; in PPCEmitCmp()
924 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD; in PPCEmitCmp()
926 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI; in PPCEmitCmp()
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
1806 unsigned DestReg, bool IsZExt) { in PPCEmitIntExt() argument
1813 if (!IsZExt) { in PPCEmitIntExt()
1903 bool IsZExt = isa<ZExtInst>(I); in SelectIntExt() local
1929 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt)) in SelectIntExt()
2310 bool IsZExt = false; in tryToFoldLoadIntoMI() local
2317 IsZExt = true; in tryToFoldLoadIntoMI()
2328 IsZExt = true; in tryToFoldLoadIntoMI()
2366 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt, in tryToFoldLoadIntoMI()