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Searched refs:IsWrite (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUAsanInstrumentation.cpp99 Value *Addr, bool IsWrite, in generateCrashCode() argument
105 SmallString<64> TypeStr{IsWrite ? "store" : "load"}; in generateCrashCode()
154 bool IsWrite, Value *SizeArgument, in instrumentAddressImpl() argument
178 generateCrashCode(M, IRB, IntptrTy, CrashTerm, AddrLong, IsWrite, in instrumentAddressImpl()
185 TypeSize TypeStoreSize, bool IsWrite, in instrumentAddress() argument
200 M, IRB, OrigIns, InsertBefore, Addr, Alignment, FixedSize, IsWrite, in instrumentAddress()
214 instrumentAddressImpl(M, IRB, OrigIns, InsertBefore, Addr, {}, 8, IsWrite, in instrumentAddress()
216 instrumentAddressImpl(M, IRB, OrigIns, InsertBefore, LastByte, {}, 8, IsWrite, in instrumentAddress()
243 bool IsWrite = CI->getType()->isVoidTy(); in getInterestingMemoryOperands() local
245 unsigned OpOffset = IsWrite ? 1 : 0; in getInterestingMemoryOperands()
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H A DAMDGPUAsanInstrumentation.h47 TypeSize TypeStoreSize, bool IsWrite,
H A DAMDGPUSwLowerLDS.cpp1289 Operand.IsWrite, nullptr, false, false, AsanInfo.Scale, in run()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DMemProfInstrumentation.cpp175 bool IsWrite; member
199 Value *Addr, bool IsWrite);
202 bool IsWrite);
300 Access.IsWrite = false; in isInterestingMemoryAccess()
306 Access.IsWrite = true; in isInterestingMemoryAccess()
312 Access.IsWrite = true; in isInterestingMemoryAccess()
318 Access.IsWrite = true; in isInterestingMemoryAccess()
332 Access.IsWrite = true; in isInterestingMemoryAccess()
337 Access.IsWrite = false; in isInterestingMemoryAccess()
386 Type *AccessTy, bool IsWrite) { in instrumentMaskedLoadOrStore() argument
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H A DThreadSanitizer.cpp420 const bool IsWrite = isa<StoreInst>(*I); in chooseInstructionsToInstrument() local
421 Value *Addr = IsWrite ? cast<StoreInst>(I)->getPointerOperand() in chooseInstructionsToInstrument()
427 if (!IsWrite) { in chooseInstructionsToInstrument()
463 if (IsWrite) { in chooseInstructionsToInstrument()
592 const bool IsWrite = isa<StoreInst>(*II.Inst); in instrumentLoadOrStore() local
593 Value *Addr = IsWrite ? cast<StoreInst>(II.Inst)->getPointerOperand() in instrumentLoadOrStore()
606 if (IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
622 if (!IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
628 const Align Alignment = IsWrite ? cast<StoreInst>(II.Inst)->getAlign() in instrumentLoadOrStore()
633 (IsWrite ? cast<StoreInst>(II.Inst)->isVolatile() in instrumentLoadOrStore()
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H A DAddressSanitizer.cpp661 IsWrite((Packed >> kIsWriteShift) & kIsWriteMask), in ASanAccessInfo()
664 ASanAccessInfo::ASanAccessInfo(bool IsWrite, bool CompileKernel, in ASanAccessInfo() argument
666 : Packed((IsWrite << kIsWriteShift) + in ASanAccessInfo()
669 AccessSizeIndex(AccessSizeIndex), IsWrite(IsWrite), in ASanAccessInfo()
815 uint32_t TypeStoreSize, bool IsWrite,
820 uint32_t TypeStoreSize, bool IsWrite,
826 TypeSize TypeStoreSize, bool IsWrite,
834 Type *OpType, bool IsWrite,
840 bool IsWrite, size_t AccessSizeIndex,
1504 bool IsWrite = CI->getType()->isVoidTy(); in getInterestingMemoryOperands() local
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H A DHWAddressSanitizer.cpp339 int64_t getAccessInfo(bool IsWrite, unsigned AccessSizeIndex);
342 void instrumentMemAccessOutline(Value *Ptr, bool IsWrite,
346 void instrumentMemAccessInline(Value *Ptr, bool IsWrite,
940 int64_t HWAddressSanitizer::getAccessInfo(bool IsWrite, in getAccessInfo() argument
946 (IsWrite << HWASanAccessInfo::IsWriteShift) | in getAccessInfo()
978 void HWAddressSanitizer::instrumentMemAccessOutline(Value *Ptr, bool IsWrite, in instrumentMemAccessOutline() argument
984 const int64_t AccessInfo = getAccessInfo(IsWrite, AccessSizeIndex); in instrumentMemAccessOutline()
1020 void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, in instrumentMemAccessInline() argument
1026 const int64_t AccessInfo = getAccessInfo(IsWrite, AccessSizeIndex); in instrumentMemAccessInline()
1159 IRB.CreateCall(HwasanMemoryAccessCallback[O.IsWrite][AccessSizeIndex], in instrumentMemAccess()
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H A DTypeSanitizer.cpp84 bool IsWrite, Value *ShadowBase,
579 bool IsRead, bool IsWrite, Value *ShadowBase, Value *AppMemMask, in instrumentWithShadowUpdate() argument
617 if (ForceSetType || (ClWritesAlwaysSetType && IsWrite)) { in instrumentWithShadowUpdate()
696 Constant *Flags = ConstantInt::get(OrdTy, int(IsRead) | (int(IsWrite) << 1)); in instrumentWithShadowUpdate()
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Instrumentation/
H A DAddressSanitizerCommon.h28 bool IsWrite; variable
39 InterestingMemoryOperand(Instruction *I, unsigned OperandNo, bool IsWrite,
44 : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment), in IsWrite() function
H A DAddressSanitizer.h64 const bool IsWrite; member
68 LLVM_ABI ASanAccessInfo(bool IsWrite, bool CompileKernel,
/freebsd/contrib/llvm-project/compiler-rt/lib/tysan/
H A Dtysan.cpp262 bool IsWrite = flags & 2; in __tysan_check() local
264 if (IsRead && !IsWrite) in __tysan_check()
266 else if (!IsRead && IsWrite) in __tysan_check()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DLoopAccessAnalysis.cpp1271 bool IsWrite = Access.getInt(); in createCheckForAccess() local
1272 RtCheck.insert(TheLoop, Ptr, PtrExpr, AccessTy, IsWrite, DepId, ASId, PSE, in createCheckForAccess()
1315 bool IsWrite = Accesses.contains(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
1316 if (IsWrite) in canCheckPtrAtRT()
1320 AccessInfos.emplace_back(Ptr, IsWrite); in canCheckPtrAtRT()
1490 bool IsWrite = AC.getInt(); in processMemAccesses() local
1494 bool IsReadOnlyPtr = ReadOnlyPtr.contains(Ptr) && !IsWrite; in processMemAccesses()
1499 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite || in processMemAccesses()
1503 MemAccessInfo Access(Ptr, IsWrite); in processMemAccesses()
1522 if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) { in processMemAccesses()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DLoopAccessAnalysis.h276 ArrayRef<unsigned> getOrderForAccess(Value *Ptr, bool IsWrite) const { in getOrderForAccess() argument
277 auto I = Accesses.find({Ptr, IsWrite}); in getOrderForAccess()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DFunctionAttrs.cpp872 bool IsWrite = false; in determinePointerAccessAttrs() local
880 if (IsWrite && IsRead) in determinePointerAccessAttrs()
955 IsWrite = true; in determinePointerAccessAttrs()
981 IsWrite = true; in determinePointerAccessAttrs()
993 if (IsWrite && IsRead) in determinePointerAccessAttrs()
997 else if (IsWrite) in determinePointerAccessAttrs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1690 int64_t IsWrite = MI.getOperand(2).getImm(); in legalizeIntrinsic() local
1695 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit in legalizeIntrinsic()
2339 int64_t IsWrite = MI.getOperand(1).getImm(); in legalizePrefetch() local
2352 unsigned PrfOp = (IsWrite << 4) | (!IsData << 3) | (Locality << 1) | IsStream; in legalizePrefetch()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp93 bool IsWrite; member
1375 IntelSubgroups->IsWrite in generateIntelSubgroupsInst()
H A DSPIRVBuiltins.td1199 bit IsWrite = !or(!eq(operation, OpSubgroupBlockWriteINTEL),
1208 let Fields = ["Name", "Opcode", "IsBlock", "IsWrite", "IsMedia"];
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp959 StringRef Name = AccessInfo.IsWrite ? "store" : "load"; in LowerASAN_CHECK_MEMACCESS()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5288 bool IsWrite = Op.getConstantOperandVal(2); in lowerPREFETCH() local
5289 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ; in lowerPREFETCH()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4258 unsigned IsWrite = Op.getConstantOperandVal(2); in LowerPREFETCH() local
4274 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit in LowerPREFETCH()
5791 unsigned IsWrite = Op.getConstantOperandVal(3); in LowerINTRINSIC_VOID() local
5795 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit in LowerINTRINSIC_VOID()