618       IsWrite((Packed >> kIsWriteShift) & kIsWriteMask),  in ASanAccessInfo()
621 ASanAccessInfo::ASanAccessInfo(bool IsWrite, bool CompileKernel,  in ASanAccessInfo()  argument
623     : Packed((IsWrite << kIsWriteShift) +  in ASanAccessInfo()
626       AccessSizeIndex(AccessSizeIndex), IsWrite(IsWrite),  in ASanAccessInfo()
767                          uint32_t TypeStoreSize, bool IsWrite,
772                                        uint32_t TypeStoreSize, bool IsWrite,
778                                         TypeSize TypeStoreSize, bool IsWrite,
786                                    Type *OpType, bool IsWrite,
792                                  bool IsWrite, size_t AccessSizeIndex,
1437       bool IsWrite = CI->getType()->isVoidTy();  in getInterestingMemoryOperands()  local
1439       unsigned OpOffset = IsWrite ? 1 : 0;  in getInterestingMemoryOperands()
1440       if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)  in getInterestingMemoryOperands()
1446       Type *Ty = IsWrite ? CI->getArgOperand(0)->getType() : CI->getType();  in getInterestingMemoryOperands()
1452       Interesting.emplace_back(I, OpOffset, IsWrite, Ty, Alignment, Mask);  in getInterestingMemoryOperands()
1457       bool IsWrite = CI->getIntrinsicID() == Intrinsic::masked_compressstore;  in getInterestingMemoryOperands()  local
1458       unsigned OpOffset = IsWrite ? 1 : 0;  in getInterestingMemoryOperands()
1459       if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)  in getInterestingMemoryOperands()
1465       Type *Ty = IsWrite ? CI->getArgOperand(0)->getType() : CI->getType();  in getInterestingMemoryOperands()
1474       Interesting.emplace_back(I, OpOffset, IsWrite, Ty, Alignment, TrueMask,  in getInterestingMemoryOperands()
1484       bool IsWrite = CI->getType()->isVoidTy();  in getInterestingMemoryOperands()  local
1485       if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)  in getInterestingMemoryOperands()
1488       Type *Ty = IsWrite ? CI->getArgOperand(0)->getType() : CI->getType();  in getInterestingMemoryOperands()
1502       Interesting.emplace_back(I, PtrOpNo, IsWrite, Ty, Alignment,  in getInterestingMemoryOperands()
1511       bool IsWrite = IID == Intrinsic::vp_scatter;  in getInterestingMemoryOperands()  local
1512       if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)  in getInterestingMemoryOperands()
1515       Type *Ty = IsWrite ? CI->getArgOperand(0)->getType() : CI->getType();  in getInterestingMemoryOperands()
1517       Interesting.emplace_back(I, PtrOpNo, IsWrite, Ty, Alignment,  in getInterestingMemoryOperands()
1594                                 TypeSize TypeStoreSize, bool IsWrite,  in doInstrumentAddress()  argument
1610                                        FixedSize, IsWrite, nullptr, UseCalls,  in doInstrumentAddress()
1615                                          IsWrite, nullptr, UseCalls, Exp, RTCI);  in doInstrumentAddress()
1621     MaybeAlign Alignment, unsigned Granularity, Type *OpType, bool IsWrite,  in instrumentMaskedLoadOrStore()  argument
1679                         Alignment, Granularity, ElemTypeSize, IsWrite,  in instrumentMaskedLoadOrStore()
1723   if (O.IsWrite)  in instrumentMop()
1732                                 Granularity, O.OpType, O.IsWrite, nullptr,  in instrumentMop()
1736                         Granularity, O.TypeStoreSize, O.IsWrite, nullptr,  in instrumentMop()
1742                                                  Value *Addr, bool IsWrite,  in generateCrashCode()  argument
1752       Call = RTCI.createRuntimeCall(IRB, AsanErrorCallbackSized[IsWrite][0],  in generateCrashCode()
1755       Call = RTCI.createRuntimeCall(IRB, AsanErrorCallbackSized[IsWrite][1],  in generateCrashCode()
1760           IRB, AsanErrorCallback[IsWrite][0][AccessSizeIndex], Addr);  in generateCrashCode()
1763           IRB, AsanErrorCallback[IsWrite][1][AccessSizeIndex], {Addr, ExpVal});  in generateCrashCode()
1790     uint32_t TypeStoreSize, bool IsWrite, Value *SizeArgument) {  in instrumentAMDGPUAddress()  argument
1837                                          uint32_t TypeStoreSize, bool IsWrite,  in instrumentAddress()  argument
1843                                            TypeStoreSize, IsWrite, SizeArgument);  in instrumentAddress()
1850   const ASanAccessInfo AccessInfo(IsWrite, CompileKernel, AccessSizeIndex);  in instrumentAddress()
1853     const ASanAccessInfo AccessInfo(IsWrite, CompileKernel, AccessSizeIndex);  in instrumentAddress()
1866           IRB, AsanMemoryAccessCallback[IsWrite][0][AccessSizeIndex], AddrLong);  in instrumentAddress()
1869           IRB, AsanMemoryAccessCallback[IsWrite][1][AccessSizeIndex],  in instrumentAddress()
1918       CrashTerm, AddrLong, IsWrite, AccessSizeIndex, SizeArgument, Exp, RTCI);  in instrumentAddress()
1929     TypeSize TypeStoreSize, bool IsWrite, Value *SizeArgument, bool UseCalls,  in instrumentUnusualSizeOrAlignment()  argument
1938       RTCI.createRuntimeCall(IRB, AsanMemoryAccessCallbackSized[IsWrite][0],  in instrumentUnusualSizeOrAlignment()
1942           IRB, AsanMemoryAccessCallbackSized[IsWrite][1],  in instrumentUnusualSizeOrAlignment()
1949     instrumentAddress(I, InsertBefore, Addr, {}, 8, IsWrite, Size, false, Exp,  in instrumentUnusualSizeOrAlignment()
1951     instrumentAddress(I, InsertBefore, LastByte, {}, 8, IsWrite, Size, false,  in instrumentUnusualSizeOrAlignment()