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Searched refs:IsThumb2 (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td1032 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
1042 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
1056 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
1368 Requires<[IsThumb2]>,
1377 Requires<[HasDSP, IsThumb2]>,
1386 Requires<[HasDSP, IsThumb2]>,
1975 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1976 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1977 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1989 Requires<[IsThumb2,HasV7,HasMP]>;
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H A DARMInstrFormats.td380 : InstAlias<Asm, Result, EmitPriority>, Requires<[IsThumb2]>;
383 Requires<[IsThumb2,UseNegativeImmediates]>;
499 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
547 list<Predicate> Predicates = [IsThumb2];
1144 list<Predicate> Predicates = [IsThumb2, HasDSP];
1147 list<Predicate> Predicates = [IsThumb2, UseMulOps, HasDSP];
1354 list<Predicate> Predicates = [IsThumb2];
1375 list<Predicate> Predicates = [IsThumb2];
1388 list<Predicate> Predicates = [IsThumb2];
1475 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> {
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H A DARMISelDAGToDAG.cpp5493 bool IsThumb2 = Subtarget->isThumb2(); in tryReadRegister() local
5507 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC; in tryReadRegister()
5512 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC; in tryReadRegister()
5531 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked, in tryReadRegister()
5585 ReplaceNode(N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, in tryReadRegister()
5594 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, DL, in tryReadRegister()
5608 bool IsThumb2 = Subtarget->isThumb2(); in tryWriteRegister() local
5621 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR; in tryWriteRegister()
5626 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR; in tryWriteRegister()
5646 N, CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked, in tryWriteRegister()
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H A DARMPredicates.td158 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
H A DARMISelLowering.cpp11340 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) { in getLdOpcode() argument
11348 if (IsThumb2) in getLdOpcode()
11359 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) { in getStOpcode() argument
11367 if (IsThumb2) in getStOpcode()
11381 unsigned AddrOut, bool IsThumb1, bool IsThumb2) { in emitPostLd() argument
11382 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2); in emitPostLd()
11401 } else if (IsThumb2) { in emitPostLd()
11422 unsigned AddrOut, bool IsThumb1, bool IsThumb2) { in emitPostSt() argument
11423 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2); in emitPostSt()
11443 } else if (IsThumb2) { in emitPostSt()
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H A DARMInstrVFP.td1322 Requires<[IsThumb2, HasV6T2]>;
1328 Requires<[IsThumb2]>;
H A DARMInstrThumb.td341 let Predicates = [IsThumb2, HasV8];