Lines Matching refs:IsThumb2
1032 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
1042 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
1056 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
1368 Requires<[IsThumb2]>,
1377 Requires<[HasDSP, IsThumb2]>,
1386 Requires<[HasDSP, IsThumb2]>,
1975 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1976 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1977 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1989 Requires<[IsThumb2,HasV7,HasMP]>;
1992 Requires<[IsThumb2,HasV7,HasMP]>;
1995 Requires<[IsThumb2,HasV7,HasMP]>;
1999 Requires<[IsThumb2,HasV7]>;
2002 Requires<[IsThumb2,HasV7]>;
2005 Requires<[IsThumb2,HasV7]>;
2026 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
2027 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
2033 Requires<[IsThumb2,HasV7]>;
2040 Requires<[IsThumb2,HasV7]>;
2045 Requires<[IsThumb2,HasV7]>;
2392 // Requires<[HasDSP, IsThumb2]>;
2395 Requires<[HasDSP, IsThumb2]>;
2527 Requires<[IsThumb2, HasDSP]> {
2542 Requires<[IsThumb2, HasDSP]> {
2680 Requires<[IsThumb2, HasDSP]> {
2687 Requires<[IsThumb2, HasDSP]>;
2711 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2718 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
2726 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2732 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
3016 Requires<[IsThumb2]>;
3051 Requires<[IsThumb2, UseMulOps]>,
3080 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;
3090 Requires<[IsThumb2, HasDSP]>,
3108 Requires<[IsThumb2, HasDSP, UseMulOps]>,
3128 Requires<[IsThumb2, HasDSP]>,
3175 Requires<[IsThumb2, HasDSP, UseMulOps]>,
3224 Requires<[IsThumb2, HasDSP]>;
3226 Requires<[IsThumb2, HasDSP]>;
3228 Requires<[IsThumb2, HasDSP]>;
3230 Requires<[IsThumb2, HasDSP]>;
3248 Requires<[IsThumb2, HasDSP]>,
3266 Requires<[IsThumb2, HasDSP]>;
3279 Requires<[IsThumb2, HasDSP]>,
3376 Requires<[HasDSP, IsThumb2]>,
3392 Requires<[HasDSP, IsThumb2]>;
3395 Requires<[HasDSP, IsThumb2]>;
3405 Requires<[HasDSP, IsThumb2]>,
3424 Requires<[HasDSP, IsThumb2]>;
3427 Requires<[HasDSP, IsThumb2]>;
3431 Requires<[HasDSP, IsThumb2]>;
3445 Requires<[IsThumb2, HasCRC]> {
3645 Requires<[IsThumb2, HasSB]>, Sched<[]> {
3714 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteLd]> {
3795 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteST]> {
3906 Requires<[IsThumb2, HasVFP2]>;
3917 Requires<[IsThumb2, NoVFP]>;
4037 Requires<[IsThumb2]>, Sched<[WriteBr]>;
4061 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
4106 Requires<[IsThumb2, IsNotMClass]> {
4151 let Predicates = [IsThumb2, HasV8];
4154 let Predicates = [IsThumb2, HasRAS];
4157 let Predicates = [IsThumb2, HasRAS];
4168 def : InstAlias<"clrbhb$p", (t2HINT 22, pred:$p), 0>, Requires<[IsThumb2, HasV8]>;
4169 def : InstAlias<"clrbhb$p", (t2HINT 22, pred:$p), 1>, Requires<[IsThumb2, HasV8, HasCLRBHB]>;
4186 []>, Requires<[IsThumb2, HasTrustZone]> {
4196 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
4212 Requires<[IsThumb2,IsNotMClass]> {
4245 Requires<[IsThumb2,IsNotMClass]> {
4272 Requires<[IsThumb2,IsNotMClass]> {
4289 Requires<[IsThumb2, HasVirtualization]>;
4294 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
4332 Requires<[IsThumb2, UseMovtInPic]>;
4335 Requires<[IsThumb2, UseMovt]>;
4367 Requires<[IsThumb2]>;
4373 NoItinerary, []>, Requires<[IsThumb2]>;
4464 … 1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4465 …, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4469 … 0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4470 …, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4483 []>, Requires<[IsThumb2,IsNotMClass]> {
4493 []>, Requires<[IsThumb2,IsNotMClass]> {
4546 Requires<[IsThumb2,IsNotMClass]> {
4666 let Predicates = [IsThumb2, PreV8];
4683 let Predicates = [IsThumb2, PreV8];
4707 let Predicates = [IsThumb2, PreV8];
4716 let Predicates = [IsThumb2, PreV8];
4745 let Predicates = [IsThumb2, PreV8];
4771 let Predicates = [IsThumb2, PreV8];
4778 Requires<[IsThumb2, IsReadTPTPIDRURW]>;
4780 Requires<[IsThumb2, IsReadTPTPIDRURO]>;
4782 Requires<[IsThumb2, IsReadTPTPIDRPRW]>;
4790 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4847 Requires<[IsThumb2]>;
4849 Requires<[IsThumb2]>;
4851 Requires<[HasDSP, IsThumb2]>;
4854 Requires<[HasDSP, IsThumb2]>;
4857 Requires<[HasDSP, IsThumb2]>;
4861 Requires<[IsThumb2]>;
4863 Requires<[IsThumb2]>;
4866 Requires<[HasDSP, IsThumb2]>;
4869 Requires<[HasDSP, IsThumb2]>;
5095 def : InstAlias<"ssbb", (t2DSB 0x0, 14, zero_reg), 1>, Requires<[HasDB, IsThumb2]>;
5096 def : InstAlias<"pssbb", (t2DSB 0x4, 14, zero_reg), 1>, Requires<[HasDB, IsThumb2]>;
5161 Requires<[HasDSP, IsThumb2]>;
5164 Requires<[HasDSP, IsThumb2]>;
5250 Requires<[HasDSP, IsThumb2]>;
5253 Requires<[HasDSP, IsThumb2]>;
5256 Requires<[HasDSP, IsThumb2]>;
5259 Requires<[HasDSP, IsThumb2]>;
5272 Requires<[HasDSP, IsThumb2]>;
5275 Requires<[HasDSP, IsThumb2]>;
5278 Requires<[HasDSP, IsThumb2]>;
5281 Requires<[HasDSP, IsThumb2]>;
5297 Requires<[HasDSP, IsThumb2]>;
5305 Requires<[HasDSP, IsThumb2]>;
5474 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5480 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5555 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5606 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB] in {
5775 let Predicates = [IsThumb2, HasV8_1MMainline, HasPACBTI] in {
5854 Requires<[IsThumb2]>, Sched<[WriteBrL]>;