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Searched refs:IsStore (Results 1 – 25 of 38) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp157 bool IsStore = false; in emitInstruction() local
159 &IsStore); in emitInstruction()
165 bool MaskAfter = IsSPFirstOperand && !IsStore; in emitInstruction()
210 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
211 if (IsStore) in isBasePlusOffsetMemoryAccess()
212 *IsStore = false; in isBasePlusOffsetMemoryAccess()
242 if (IsStore) in isBasePlusOffsetMemoryAccess()
243 *IsStore = true; in isBasePlusOffsetMemoryAccess()
250 if (IsStore) in isBasePlusOffsetMemoryAccess()
251 *IsStore = true; in isBasePlusOffsetMemoryAccess()
H A DMipsMCNaCl.h21 bool *IsStore = nullptr);
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp74 unsigned int IsStore : 1; member
365 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
371 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
681 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
698 !SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
703 if (SwapVector[UseOfUseIdx].IsStore) { in recordUnoptimizableWebs()
720 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
728 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
794 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
1006 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kCollapseMOVEMPass.cpp205 bool IsStore = false) { in ProcessMI() argument
210 if (State.isStore() == IsStore && State.getBase() == Reg && in ProcessMI()
219 return ProcessMI(MBB, MI, State, Mask, Offset, Reg, IsStore); in ProcessMI()
228 IsStore ? State.setStore() : State.setLoad(); in ProcessMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td35 bit IsStore = false;
50 let TSFlags{5} = IsStore;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp405 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
412 if (IsStore && MI->mayLoad()) in canHoistLoadStoreTo()
454 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
464 if (IsStore) { in changeToAddrMode()
471 if (IsStore) in changeToAddrMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp28 unsigned IsStore : 1; member
272 if (VXMO->IsStore) { in getSchedClassID()
285 if (VXMO->IsStore) { in getSchedClassID()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td991 bit IsStore = ?;
1351 let IsStore = true;
1356 let IsStore = true;
1363 let IsStore = true;
1368 let IsStore = true;
1373 let IsStore = true;
1378 let IsStore = true;
1383 let IsStore = true;
1388 let IsStore = true;
1393 let IsStore = true;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp1462 bool IsStore = MI->mayStore(); in spillVGPRtoAGPR() local
1466 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
1467 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
1480 unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 in spillVGPRtoAGPR()
1499 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
1502 int LoadStoreOp = IsStore ? in buildMUBUFOffsetLoadStore()
1531 bool IsStore = TII->get(LoadStoreOp).mayStore(); in getFlatScratchSpillOpcode() local
1542 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in getFlatScratchSpillOpcode()
1546 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR in getFlatScratchSpillOpcode()
1550 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR in getFlatScratchSpillOpcode()
[all …]
H A DAMDGPUInstructions.td445 let IsStore = 1;
546 let IsStore = 1, AddressSpaces = !cast<AddressSpaceList>("StoreAddress_"#as).AddrSpaces in {
570 } // End let IsStore = 1, AddressSpaces = ...
711 let IsStore = 1;
716 let IsStore = 1;
H A DSIInstrInfo.td550 let IsStore = 1;
556 let IsStore = 1;
562 let IsStore = 1;
568 let IsStore = 1;
574 let IsStore = 1;
578 let IsStore = 1, AddressSpaces = StoreAddress_local.AddrSpaces in {
590 let IsStore = 1;
596 let IsStore = 1;
616 let IsStore = 1;
622 let IsStore = 1;
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp156 const bool IsStore = GenericOpc == TargetOpcode::G_STORE; in selectLoadStoreOp() local
161 return IsStore ? PPC::STW : PPC::LWZ; in selectLoadStoreOp()
163 return IsStore ? PPC::STD : PPC::LD; in selectLoadStoreOp()
171 return IsStore ? PPC::STFS : PPC::LFS; in selectLoadStoreOp()
173 return IsStore ? PPC::STFD : PPC::LFD; in selectLoadStoreOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.cpp363 bool IsStore = MI.getOperand(0).isReg() && MI.getOperand(1).isReg(); in optimizeMOV() local
364 unsigned AddrBase = IsStore; in optimizeMOV()
365 unsigned RegOp = IsStore ? 0 : 5; in optimizeMOV()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp461 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
462 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
463 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
480 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGAtomic.cpp1268 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
1296 if (IsStore) in EmitAtomicExpr()
1308 if (IsLoad || IsStore) in EmitAtomicExpr()
1332 if (!IsStore) in EmitAtomicExpr()
1336 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1353 if (!IsStore) { in EmitAtomicExpr()
1371 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_sve.td316 def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfdbm", [IsStore, VerifyRuntimeMode], Mem…
317 def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore, VerifyRuntimeMode], MemEl…
318 def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore, VerifyRuntimeMode], MemEl…
319 def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore, VerifyRuntimeMode], MemEl…
320 def SVST1H_U : MInst<"svst1h[_{d}]", "vPFd", "UiUl", [IsStore, VerifyRuntimeMode], MemEl…
321 def SVST1W_S : MInst<"svst1w[_{d}]", "vPCd", "l", [IsStore, VerifyRuntimeMode], MemEl…
322 def SVST1W_U : MInst<"svst1w[_{d}]", "vPGd", "Ul", [IsStore, VerifyRuntimeMode], MemEl…
325 def SVST1_VNUM : MInst<"svst1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfdbm", [IsStore, VerifyRuntim…
326 def SVST1B_VNUM_S : MInst<"svst1b_vnum[_{d}]", "vPAld", "sil", [IsStore, VerifyRuntimeM…
327 def SVST1B_VNUM_U : MInst<"svst1b_vnum[_{d}]", "vPEld", "UsUiUl", [IsStore, VerifyRuntimeM…
[all …]
H A DTargetBuiltins.h387 bool isStore() const { return Flags & IsStore; } in isStore()
H A Darm_sve_sme_incl.td208 def IsStore : FlagType<0x00004000>;
H A Darm_sme.td65 [IsStore, IsOverloadNone, IsStreaming, IsInZA],
69 [IsStore, IsOverloadNone, IsStreaming, IsInZA],
73 [IsStore, IsOverloadNone, IsStreaming, IsInZA],
77 [IsStore, IsOverloadNone, IsStreaming, IsInZA],
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp189 bool IsStore = (THType == AMDGPU::CPol::TH_TYPE_STORE); in printTH() local
207 if (!IsStore && TH == AMDGPU::CPol::TH_RESERVED) in printTH()
210 O << (IsStore ? "TH_STORE_" : "TH_LOAD_"); in printTH()
220 : (IsStore ? "WB" : "LU")); in printTH()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp829 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
830 if (!IsLoad && !IsStore) in canMoveMemTo()
851 bool Conflict = (L && IsStore) || S; in canMoveMemTo()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.h135 bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const override;
H A DX86InstrFragments.td872 let IsStore = true;
878 let IsStore = true;
884 let IsStore = true;
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaRISCV.cpp1359 bool IsStore = BuiltinID == RISCV::BI__builtin_riscv_ntl_store; in CheckBuiltinFunctionCall() local
1360 unsigned NumArgs = IsStore ? 3 : 2; in CheckBuiltinFunctionCall()
1400 if (!IsStore) { in CheckBuiltinFunctionCall()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp768 bool IsStore) const { in hasConditionalLoadStoreForType()
769 return TTIImpl->hasConditionalLoadStoreForType(Ty, IsStore); in hasConditionalLoadStoreForType()

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