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Searched refs:IsRV32 (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZk.td82 let Predicates = [HasStdExtZknd, IsRV32] in {
85 } // Predicates = [HasStdExtZknd, IsRV32]
100 let Predicates = [HasStdExtZkne, IsRV32] in {
103 } // Predicates = [HasStdExtZkne, IsRV32]
117 let Predicates = [HasStdExtZknh, IsRV32] in {
124 } // [HasStdExtZknh, IsRV32]
152 let Predicates = [HasStdExtZknd, IsRV32] in {
155 } // Predicates = [HasStdExtZknd, IsRV32]
170 let Predicates = [HasStdExtZkne, IsRV32] in {
173 } // Predicates = [HasStdExtZkne, IsRV32]
[all...]
H A DRISCVInstrInfoXCV.td41 let Predicates = [HasVendorXCVbitmanip, IsRV32],
98 let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0,
125 } // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0...
127 let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
147 } // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0...
149 let Predicates = [HasVendorXCVmac, IsRV32] in {
162 } // Predicates = [HasVendorXCVmac, IsRV32]
201 let Predicates = [HasVendorXCValu, IsRV32],
252 } // Predicates = [HasVendorXCValu, IsRV32],
255 let Predicates = [HasVendorXCValu, IsRV32],
[all...]
H A DRISCVInstrInfoD.td63 def Zdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx", [HasStdExtZdinx, IsRV32],
221 let Predicates = [HasStdExtZdinx, IsRV32] in {
233 } // Predicates = [HasStdExtZdinx, IsRV32]
256 let Predicates = [HasStdExtZdinx, IsRV32] in {
262 } // Predicates = [HasStdExtZdinx, IsRV32]
264 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
349 let Predicates = [HasStdExtZdinx, IsRV32] in {
384 } // Predicates = [HasStdExtZdinx, IsRV32]
450 let Predicates = [HasStdExtZdinx, IsRV32] in {
468 } // Predicates = [HasStdExtZdinx, IsRV32]
[all …]
H A DRISCVInstrInfoC.td335 Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
369 Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
413 Predicates = [HasStdExtCOrZca, IsRV32] in
521 Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
579 Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
730 let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
874 let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
877 } // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
894 let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
897 } // Predicates = [HasStdExtC, HasStdExtF, IsRV32]
[all …]
H A DRISCVInstrInfoZb.td418 let Predicates = [HasStdExtZbb, IsRV32] in {
421 } // Predicates = [HasStdExtZbb, IsRV32]
428 let Predicates = [HasStdExtZbbOrZbkb, IsRV32] in {
431 } // Predicates = [HasStdExtZbbOrZbkb, IsRV32]
447 let Predicates = [HasStdExtZbkb, IsRV32] in {
452 } // Predicates = [HasStdExtZbkb, IsRV32]
484 let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV32] in {
486 } // Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV32]
577 let Predicates = [HasStdExtZbkb, IsRV32] in {
581 } // Predicates = [HasStdExtZbkb, IsRV32]
[all …]
H A DRISCVInstrInfoZfa.td126 let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
138 } // Predicates = [HasStdExtZfa, HasStdExtD, IsRV32]
236 let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
H A DRISCVInstrInfoZa.td62 let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32Zacas" in {
64 } // Predicates = [HasStdExtZacas, IsRV32]
H A DRISCVInstrInfoZfh.td63 [HasStdExtZhinx, HasStdExtZdinx, IsRV32],
66 [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32],
254 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
304 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
576 let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32] in {
586 } // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32]
H A DRISCVInstrInfoXTHead.td642 let Predicates = [HasVendorXTHeadMac, IsRV32] in {
649 } // Predicates = [HasVendorXTHeadMac, IsRV32]
H A DRISCVFeatures.td1280 : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
1286 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
H A DRISCVInstrInfo.td961 let Predicates = [IsRV32] in {
965 } // Predicates = [IsRV32]
1923 let Predicates = [IsRV32], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
H A DRISCVInstrInfoF.td513 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A DELF_riscv.cpp501 bool IsRV32; member
528 Aux.Config.IsRV32 = G.getTargetTriple().isRISCV32(); in initRelaxAux()
607 } else if (Config.HasRVC && Config.IsRV32 && isInt<12>(Displace) && RD == 1) { in relaxCall()