Searched refs:IsROTL (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2265 bool IsROTL = (Op.getOpcode() == ISD::ROTL); in SimplifyDemandedBits() local
2277 APInt Demanded0 = DemandedBits.rotr(IsROTL ? Amt : RevAmt); in SimplifyDemandedBits()
2288 DemandedBits.countr_zero() >= (IsROTL ? Amt : RevAmt)) { in SimplifyDemandedBits()
2289 Op1 = TLO.DAG.getConstant(IsROTL ? Amt : RevAmt, dl, Op1.getValueType()); in SimplifyDemandedBits()
2293 DemandedBits.countl_zero() >= (IsROTL ? RevAmt : Amt)) { in SimplifyDemandedBits()
2294 Op1 = TLO.DAG.getConstant(IsROTL ? RevAmt : Amt, dl, Op1.getValueType()); in SimplifyDemandedBits()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 31378 bool IsROTL = Opcode == ISD::ROTL; in LowerRotate() local
31394 unsigned RotOpc = IsROTL ? X86ISD::VROTLI : X86ISD::VROTRI; in LowerRotate()
31406 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
31412 if (!IsROTL) { in LowerRotate()
31441 assert(IsROTL && "Only ROTL expected"); in LowerRotate()
31460 uint64_t ShlAmt = IsROTL ? RotAmt : (EltSizeInBits - RotAmt); in LowerRotate()
31461 uint64_t SrlAmt = IsROTL ? (EltSizeInBits - RotAmt) : RotAmt; in LowerRotate()
31493 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
31496 unsigned ShiftX86Opc = IsROTL ? X86ISD::VSHLI : X86ISD::VSRLI; in LowerRotate()
31503 return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL); in LowerRotate()
[all …]
|