Lines Matching refs:IsROTL
30161 bool IsROTL = Opcode == ISD::ROTL; in LowerRotate() local
30177 unsigned RotOpc = IsROTL ? X86ISD::VROTLI : X86ISD::VROTRI; in LowerRotate()
30189 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
30195 if (!IsROTL) { in LowerRotate()
30224 assert(IsROTL && "Only ROTL expected"); in LowerRotate()
30243 uint64_t ShlAmt = IsROTL ? RotAmt : (EltSizeInBits - RotAmt); in LowerRotate()
30244 uint64_t SrlAmt = IsROTL ? (EltSizeInBits - RotAmt) : RotAmt; in LowerRotate()
30276 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
30279 unsigned ShiftX86Opc = IsROTL ? X86ISD::VSHLI : X86ISD::VSRLI; in LowerRotate()
30286 return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL); in LowerRotate()
30291 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate()
30306 return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL); in LowerRotate()
30331 if (IsROTL) in LowerRotate()
30356 if (!IsROTL && !useVPTERNLOG(Subtarget, VT)) { in LowerRotate()
30358 IsROTL = true; in LowerRotate()
30361 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate()
30362 unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL; in LowerRotate()
30410 SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt); in LowerRotate()
30411 SDValue SRL = DAG.getNode(IsROTL ? ISD::SRL : ISD::SHL, DL, VT, R, AmtR); in LowerRotate()
30416 if (!IsROTL) { in LowerRotate()
30418 IsROTL = true; in LowerRotate()
30424 assert(IsROTL && "Only ROTL supported"); in LowerRotate()