Searched refs:IsPre (Results 1 – 8 of 8) sorted by relevance
1593 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad() local1605 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost; in tryIndexedLoad()1608 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1610 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in tryIndexedLoad()1612 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1621 Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost; in tryIndexedLoad()1623 Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost; in tryIndexedLoad()1625 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in tryIndexedLoad()1634 Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost; in tryIndexedLoad()1636 Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost; in tryIndexedLoad()[all …]
826 bool IsPre, MachineRegisterInfo &MRI) const override;
27123 Register Offset, bool IsPre, in isIndexingLegal() argument
5554 bool IsPre = ExtLd.isPre(); in selectIndexedExtLoad() local5573 Opc = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost; in selectIndexedExtLoad()5575 Opc = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost; in selectIndexedExtLoad()5578 Opc = IsPre ? AArch64::LDRBpre : AArch64::LDRBpost; in selectIndexedExtLoad()5582 Opc = IsPre ? AArch64::LDRBBpre : AArch64::LDRBBpost; in selectIndexedExtLoad()5589 Opc = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost; in selectIndexedExtLoad()5591 Opc = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost; in selectIndexedExtLoad()5594 Opc = IsPre ? AArch64::LDRHpre : AArch64::LDRHpost; in selectIndexedExtLoad()5598 Opc = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in selectIndexedExtLoad()5604 Opc = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in selectIndexedExtLoad()[all …]
62 bool IsPre = false; member
840 bool IsPre = AM == ISD::PRE_INC; in tryIndexedLoad() local857 if (LoadVT == MVT::i8 && IsPre) in tryIndexedLoad()861 else if (LoadVT == MVT::i16 && IsPre) in tryIndexedLoad()865 else if (LoadVT == MVT::i32 && IsPre) in tryIndexedLoad()869 else if (LoadVT == MVT::i64 && IsPre) in tryIndexedLoad()
1500 MatchInfo.IsPre = findPreIndexCandidate(LdSt, MatchInfo.Addr, MatchInfo.Base, in matchCombineIndexedLoadStore()1502 if (!MatchInfo.IsPre && in matchCombineIndexedLoadStore()1537 MIB.addImm(MatchInfo.IsPre); in applyCombineIndexedLoadStore()
3988 bool IsPre, MachineRegisterInfo &MRI) const { in isIndexingLegal() argument