Searched refs:IsPre (Results 1 – 8 of 8) sorted by relevance
1584 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad() local1594 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost; in tryIndexedLoad()1597 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1599 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in tryIndexedLoad()1601 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1610 Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost; in tryIndexedLoad()1612 Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost; in tryIndexedLoad()1614 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in tryIndexedLoad()1623 Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost; in tryIndexedLoad()1625 Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost; in tryIndexedLoad()[all …]
1311 bool IsPre, MachineRegisterInfo &MRI) const override;
25649 Register Offset, bool IsPre, in isIndexingLegal() argument
61 bool IsPre = false; member
766 bool IsPre = AM == ISD::PRE_INC; in tryIndexedLoad() local783 if (LoadVT == MVT::i8 && IsPre) in tryIndexedLoad()787 else if (LoadVT == MVT::i16 && IsPre) in tryIndexedLoad()791 else if (LoadVT == MVT::i32 && IsPre) in tryIndexedLoad()795 else if (LoadVT == MVT::i64 && IsPre) in tryIndexedLoad()
5417 bool IsPre = ExtLd.isPre(); in selectIndexedExtLoad() local5430 Opc = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost; in selectIndexedExtLoad()5432 Opc = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost; in selectIndexedExtLoad()5435 Opc = IsPre ? AArch64::LDRBBpre : AArch64::LDRBBpost; in selectIndexedExtLoad()5442 Opc = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost; in selectIndexedExtLoad()5444 Opc = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost; in selectIndexedExtLoad()5447 Opc = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in selectIndexedExtLoad()5453 Opc = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in selectIndexedExtLoad()5456 Opc = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in selectIndexedExtLoad()
1432 MatchInfo.IsPre = findPreIndexCandidate(LdSt, MatchInfo.Addr, MatchInfo.Base, in matchCombineIndexedLoadStore()1434 if (!MatchInfo.IsPre && in matchCombineIndexedLoadStore()1469 MIB.addImm(MatchInfo.IsPre); in applyCombineIndexedLoadStore()
3837 bool IsPre, MachineRegisterInfo &MRI) const { in isIndexingLegal() argument