| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.h | 99 bool IsPPC64; variable
269 return IsPPC64 ? 8 : 4; in descriptorTOCAnchorOffset()
275 return IsPPC64 ? 16 : 8; in descriptorEnvironmentPointerOffset()
281 return IsPPC64 ? PPC::X11 : PPC::R11; in getEnvironmentPointerRegister()
287 return IsPPC64 ? PPC::X2 : PPC::R2; in getTOCPointerRegister()
293 return IsPPC64 ? PPC::X13 : PPC::R13; in getThreadPointerRegister()
297 return IsPPC64 ? PPC::X1 : PPC::R1; in getStackPointerRegister()
300 bool isXRaySupported() const override { return IsPPC64 && IsLittleEndian; } in isXRaySupported()
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| H A D | PPCSubtarget.cpp | 59 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || in PPCSubtarget()
107 if (IsPPC64 && has64BitSupport()) in initSubtargetFeatures()
113 if (HasSPE && IsPPC64) in initSubtargetFeatures()
129 if (!TargetTriple.isOSAIX() || !IsPPC64) in initSubtargetFeatures()
146 if (HasAIXShLibTLSModelOpt && (!TargetTriple.isOSAIX() || !IsPPC64)) in initSubtargetFeatures()
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| H A D | PPCAsmPrinter.cpp | 813 const bool IsPPC64 = Subtarget->isPPC64(); in emitInstruction() local
859 [IsPPC64, getTOCRelocAdjustedExprForXCOFF, in emitInstruction()
862 const unsigned EntryByteSize = IsPPC64 ? 8 : 4; in emitInstruction()
1105 TmpInst.setOpcode((!IsPPC64) ? (PPC::LA) : (PPC::LA8)); in emitInstruction()
1160 assert((IsAIX && !IsPPC64 && in emitInstruction()
1204 assert(IsAIX && !IsPPC64 && in emitInstruction()
1339 assert(IsPPC64 && "Not supported for 32-bit PowerPC"); in emitInstruction()
1357 TmpInst.setOpcode(IsPPC64 ? PPC::LD : PPC::LWZ); in emitInstruction()
1362 MOSymbol, IsPPC64 ? PPC::S_GOT_TPREL_LO : PPC::S_GOT_TPREL); in emitInstruction()
1415 assert(IsPPC64 && "Not supported for 32-bit PowerPC"); in emitInstruction()
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| H A D | PPCInstrVSX.td | 123 def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
2457 // [HasVSX, HasP8Vector, IsBigEndian, IsPPC64]
2459 // [HasVSX, HasP8Vector, NoP9Vector, IsBigEndian, IsPPC64]
2465 // [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian, IsPPC64]
2466 // [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64]
2472 // [HasVSX, HasP9Vector, IsBigEndian, IsPPC64]
2475 // [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64]
2477 // [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64]
3415 let Predicates = [HasVSX, HasP8Vector, IsBigEndian, IsPPC64] in {
3450 } // HasVSX, HasP8Vector, IsBigEndian, IsPPC64
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| H A D | PPCISelLowering.cpp | 5252 SelectionDAG &DAG, MachineFunction &MF, bool IsPPC64, SDValue Arg, in CalculateTailCallArgDest() argument
5258 EVT VT = IsPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
5722 const bool IsPPC64 = Subtarget.isPPC64(); in buildCallOperands() local
5762 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT)); in buildCallOperands()
6860 const bool IsPPC64 = Subtarget.isPPC64(); in CC_AIX() local
6861 const unsigned PtrSize = IsPPC64 ? 8 : 4; in CC_AIX()
6884 const ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX()
6937 assert(IsPPC64 && "PPC32 should have split i64 values."); in CC_AIX()
6960 State.AllocateStack(IsPPC64 ? 8 : StoreSize, Align(4)); in CC_AIX()
7097 bool IsPPC64, in getRegClassForSVT() argument
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| H A D | PPCISelDAGToDAG.cpp | 5694 bool IsPPC64 = Subtarget->isPPC64(); in Select() local
5695 if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) && in Select()
5717 bool IsPPC64 = Subtarget->isPPC64(); in Select() local
5718 if (IsPPC64 && isInt64Immediate(N->getOperand(1), Imm64) && in Select()
6010 bool IsPPC64 = Subtarget->isPPC64(); in Select() local
6013 ? (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in Select()
6014 : (IsPPC64 ? PPC::BDZ8 : PPC::BDZ), in Select()
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| H A D | PPCInstrP10.td | 2447 let Predicates = [IsISA3_1, HasVSX, IsBigEndian, IsPPC64] in {
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 102 const bool IsPPC64; member in __anon49f2f9030111::PPCAsmParser
106 bool isPPC64() const { return IsPPC64; } in isPPC64()
147 IsPPC64(STI.getTargetTriple().isPPC64()) { in PPCAsmParser()
176 bool IsPPC64; member
211 IsPPC64 = o.IsPPC64; in PPCOperand()
244 bool isPPC64() const { return IsPPC64; } in isPPC64()
408 if (!IsPPC64) { in isDirectBr()
672 bool IsPPC64) { in CreateToken()
678 Op->IsPPC64 = IsPPC64; in CreateToken()
683 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { in CreateTokenWithStringCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | AddressSanitizer.cpp | 488 bool IsPPC64 = TargetTriple.getArch() == Triple::ppc64 || in getShadowMapping() local
537 else if (IsPPC64) in getShadowMapping()
598 Mapping.OrShadowOffset = !IsAArch64 && !IsPPC64 && !IsSystemZ && !IsPS && in getShadowMapping()
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