Lines Matching refs:IsPPC64
5707 const bool IsPPC64 = Subtarget.isPPC64(); in buildCallOperands() local
5709 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands()
5747 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT)); in buildCallOperands()
6848 const bool IsPPC64 = Subtarget.isPPC64(); in CC_AIX() local
6849 const unsigned PtrSize = IsPPC64 ? 8 : 4; in CC_AIX()
6852 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in CC_AIX()
6872 const ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX()
6925 assert(IsPPC64 && "PPC32 should have split i64 values."); in CC_AIX()
6948 State.AllocateStack(IsPPC64 ? 8 : StoreSize, Align(4)); in CC_AIX()
7085 bool IsPPC64, in getRegClassForSVT() argument
7088 assert((IsPPC64 || SVT != MVT::i64) && in getRegClassForSVT()
7097 return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in getRegClassForSVT()
7204 const bool IsPPC64 = Subtarget.isPPC64(); in LowerFormalArguments_AIX() local
7205 const unsigned PtrByteSize = IsPPC64 ? 8 : 4; in LowerFormalArguments_AIX()
7277 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7291 assert(!IsPPC64 && in LowerFormalArguments_AIX()
7365 IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in LowerFormalArguments_AIX()
7416 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX()
7457 const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32); in LowerFormalArguments_AIX()
7467 IsPPC64 ? MF.addLiveIn(GPR_64[GPRIndex], &PPC::G8RCRegClass) in LowerFormalArguments_AIX()
7516 const bool IsPPC64 = Subtarget.isPPC64(); in LowerCall_AIX() local
7518 const unsigned PtrByteSize = IsPPC64 ? 8 : 4; in LowerCall_AIX()
7543 const SDValue StackPtr = IsPPC64 ? DAG.getRegister(PPC::X1, MVT::i64) in LowerCall_AIX()
7705 assert(!IsPPC64 && in LowerCall_AIX()
7749 assert(Arg.getValueType() == MVT::f64 && CFlags.IsVarArg && !IsPPC64 && in LowerCall_AIX()