Home
last modified time | relevance | path

Searched refs:IsLE (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCAsmBackend.cpp35 bool IsLE = Endian == llvm::endianness::little; in createObjectWriter() local
39 OS, IsLE); in createObjectWriter()
45 cast<MCELFObjectTargetWriter>(std::move(TW)), OS, IsLE); in createObjectWriter()
/freebsd/contrib/llvm-project/llvm/lib/Object/
H A DDecompressor.cpp22 bool IsLE, bool Is64Bit) { in create() argument
24 if (Error Err = D.consumeCompressedHeader(Is64Bit, IsLE)) in create()
/freebsd/contrib/llvm-project/llvm/include/llvm/Object/
H A DDecompressor.h29 bool IsLE, bool Is64Bit);
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3603 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3604 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3605 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3606 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3607 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3608 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3610 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3611 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3612 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3613 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
[all …]
H A DMipsInstrInfo.td237 def IsLE : Predicate<"Subtarget->isLittle()">;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h644 bool &Swap, bool IsLE);
665 bool &Swap, bool IsLE);
685 unsigned &InsertAtByte, bool &Swap, bool IsLE);
H A DPPCISelLowering.cpp1888 bool IsLE = DAG.getDataLayout().isLittleEndian(); in isVPKUHUMShuffleMask() local
1890 if (IsLE) in isVPKUHUMShuffleMask()
1896 if (!IsLE) in isVPKUHUMShuffleMask()
1902 unsigned j = IsLE ? 0 : 1; in isVPKUHUMShuffleMask()
1919 bool IsLE = DAG.getDataLayout().isLittleEndian(); in isVPKUWUMShuffleMask() local
1921 if (IsLE) in isVPKUWUMShuffleMask()
1928 if (!IsLE) in isVPKUWUMShuffleMask()
1935 unsigned j = IsLE ? 0 : 2; in isVPKUWUMShuffleMask()
1960 bool IsLE = DAG.getDataLayout().isLittleEndian(); in isVPKUDUMShuffleMask() local
1962 if (IsLE) in isVPKUDUMShuffleMask()
[all …]
H A DPPCInstrInfo.cpp3130 bool IsLE = Subtarget.isLittleEndian(); in expandPostRAPseudo() local
3133 if (IsLE) in expandPostRAPseudo()
3138 if (IsLE) in expandPostRAPseudo()
3143 if (IsLE) in expandPostRAPseudo()
/freebsd/contrib/llvm-project/llvm/lib/ObjectYAML/
H A DMachOEmitter.cpp378 makeRelocationInfo(const MachOYAML::Relocation &R, bool IsLE) { in makeRelocationInfo()
382 if (IsLE) in makeRelocationInfo()
377 makeRelocationInfo(const MachOYAML::Relocation & R,bool IsLE) makeRelocationInfo() argument
H A DELFEmitter.cpp2109 bool IsLE = Doc.Header.Data == ELFYAML::ELF_ELFDATA(ELF::ELFDATA2LSB); in yaml2elf() local
2112 if (IsLE) in yaml2elf()
2116 if (IsLE) in yaml2elf()
/freebsd/contrib/llvm-project/llvm/lib/DWP/
H A DDWP.cpp341 bool IsLE = isa<object::ELF32LEObjectFile>(Obj) || in handleCompressedSection() local
345 Expected<Decompressor> Dec = Decompressor::create(Name, Contents, IsLE, Is64); in handleCompressedSection()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMPredicates.td222 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
H A DARMInstrThumb.td1645 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1647 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1649 Requires<[IsThumb, IsThumb1Only, IsLE]>;
H A DARMInstrNEON.td2476 let Predicates = [IsLE,HasNEON] in {
2501 let Predicates = [IsLE,HasNEON] in {
7540 let Predicates = [IsLE,HasNEON] in {
8031 let Predicates = [HasNEON,IsLE] in {
8056 let Predicates = [HasNEON,IsLE] in {
H A DARMInstrMVE.td7295 let Predicates = [HasMVEInt, IsLE] in {
7454 let Predicates = [IsLE,HasMVEInt] in {
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td315 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
3370 let Predicates = [IsLE] in {
3384 let Predicates = [IsLE] in {
3518 let Predicates = [IsLE] in {
3539 let Predicates = [IsLE] in {
3715 let Predicates = [IsLE] in {
3733 let Predicates = [IsLE] in {
4123 let Predicates = [IsLE] in {
4137 let Predicates = [IsLE, UseSTRQro] in {
4225 let Predicates = [IsLE] in {
[all …]
H A DAArch64SVEInstrInfo.td2659 let Predicates = [IsLE] in {
2963 let Predicates = [IsLE] in {
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp687 bool IsLE = DAG.getDataLayout().isLittleEndian(); in SimplifyMultipleUseDemandedBits() local
715 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyMultipleUseDemandedBits()
732 if (IsLE && (NumSrcEltBits % NumDstEltBits) == 0) { in SimplifyMultipleUseDemandedBits()
857 if (IsLE && DemandedElts == 1 && in SimplifyMultipleUseDemandedBits()
1113 bool IsLE = TLO.DAG.getDataLayout().isLittleEndian(); in SimplifyDemandedBits() local
2434 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2486 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2540 if (IsLE && IsVecInReg && DemandedElts == 1 && in SimplifyDemandedBits()
2718 unsigned EltOffset = IsLE ? i : (Scale - 1 - i); in SimplifyDemandedBits()
2738 } else if (IsLE && (NumSrcEltBits % BitWidth) == 0) { in SimplifyDemandedBits()
[all …]
H A DSelectionDAG.cpp3374 bool IsLE = getDataLayout().isLittleEndian(); in computeKnownBits() local
3393 unsigned Shifts = IsLE ? i : SubScale - 1 - i; in computeKnownBits()
3413 unsigned Shifts = IsLE ? i : NumElts - 1 - i; in computeKnownBits()
4558 bool IsLE = getDataLayout().isLittleEndian(); in ComputeNumSignBits() local
4578 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset); in ComputeNumSignBits()
6603 bool IsLE = getDataLayout().isLittleEndian(); in FoldConstantArithmetic() local
6607 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) && in FoldConstantArithmetic()
6608 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2)) { in FoldConstantArithmetic()
6631 BuildVectorSDNode::recastRawBits(IsLE, BVVT.getScalarSizeInBits(), in FoldConstantArithmetic()
H A DDAGCombiner.cpp15830 bool IsLE = DAG.getDataLayout().isLittleEndian(); in ConstantFoldBITCASTofBUILD_VECTOR() local
15831 if (!BVN->getConstantRawBits(IsLE, DstBitSize, RawBits, UndefElements)) in ConstantFoldBITCASTofBUILD_VECTOR()
20307 bool IsLE = DAG.getDataLayout().isLittleEndian(); in mergeStoresOfConstantsOrVecElts() local
20309 unsigned Idx = IsLE ? (NumStores - 1 - i) : i; in mergeStoresOfConstantsOrVecElts()
22651 bool IsLE = DAG.getDataLayout().isLittleEndian(); in visitEXTRACT_VECTOR_ELT() local
22654 unsigned BCTruncElt = IsLE ? 0 : NumElts - 1; in visitEXTRACT_VECTOR_ELT()
22668 BCTruncElt = IsLE ? 0 : XBitWidth / VecEltBitWidth - 1; in visitEXTRACT_VECTOR_ELT()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp17124 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
17130 if (!IsLE) in EmitPPCBuiltinExpr()
17141 llvm::Function *Lvs = CGM.getIntrinsic(IsLE ? Intrinsic::ppc_altivec_lvsr in EmitPPCBuiltinExpr()
17150 Op0 = IsLE ? HiLd : LoLd; in EmitPPCBuiltinExpr()
17151 Op1 = IsLE ? LoLd : HiLd; in EmitPPCBuiltinExpr()
17153 Constant *Zero = llvm::Constant::getNullValue(IsLE ? ResTy : AllElts->getType()); in EmitPPCBuiltinExpr()
17155 if (IsLE) { in EmitPPCBuiltinExpr()
17177 bool IsLE = getTarget().isLittleEndian(); in EmitPPCBuiltinExpr() local
17183 if (IsLE) { in EmitPPCBuiltinExpr()
17219 if (IsLE && Width > 1) { in EmitPPCBuiltinExpr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp8035 bool IsLE = SI.getDataLayout().isLittleEndian(); in splitMergedValStore() local
8040 const bool IsOffsetStore = (IsLE && Upper) || (!IsLE && !Upper); in splitMergedValStore()