687   bool IsLE = DAG.getDataLayout().isLittleEndian();  in SimplifyMultipleUseDemandedBits()  local
715         unsigned EltOffset = IsLE ? i : (Scale - 1 - i);  in SimplifyMultipleUseDemandedBits()
732     if (IsLE && (NumSrcEltBits % NumDstEltBits) == 0) {  in SimplifyMultipleUseDemandedBits()
857     if (IsLE && DemandedElts == 1 &&  in SimplifyMultipleUseDemandedBits()
1113   bool IsLE = TLO.DAG.getDataLayout().isLittleEndian();  in SimplifyDemandedBits()  local
2434       if (IsLE && IsVecInReg && DemandedElts == 1 &&  in SimplifyDemandedBits()
2486       if (IsLE && IsVecInReg && DemandedElts == 1 &&  in SimplifyDemandedBits()
2540     if (IsLE && IsVecInReg && DemandedElts == 1 &&  in SimplifyDemandedBits()
2718         unsigned EltOffset = IsLE ? i : (Scale - 1 - i);  in SimplifyDemandedBits()
2738     } else if (IsLE && (NumSrcEltBits % BitWidth) == 0) {  in SimplifyDemandedBits()
3086   bool IsLE = TLO.DAG.getDataLayout().isLittleEndian();  in SimplifyDemandedVectorElts()  local
3163       if (IsLE) {  in SimplifyDemandedVectorElts()
3534     if (IsLE && Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG &&  in SimplifyDemandedVectorElts()
3549       if (IsLE && DemandedSrcElts == 1 && Src.getOpcode() == ISD::AND &&  in SimplifyDemandedVectorElts()