Home
last modified time | relevance | path

Searched refs:InstRWs (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.cpp897 for (const Record *RWDef : SchedClasses[SCIdx].InstRWs) { in collectSchedClasses()
1027 const ConstRecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs; in createInstRWClass()
1057 SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef); in createInstRWClass()
1077 for (const Record *OldRWDef : SchedClasses[OldSCIdx].InstRWs) { in createInstRWClass()
1089 SC.InstRWs.push_back(OldRWDef); in createInstRWClass()
1095 SC.InstRWs.push_back(InstRWDef); in createInstRWClass()
1187 if (!SchedClasses[Idx].InstRWs.empty()) in inferSchedClasses()
1223 for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) { in inferFromInstRWs()
1224 assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!"); in inferFromInstRWs()
1225 const Record *Rec = SchedClasses[SCIdx].InstRWs[I]; in inferFromInstRWs()
[all …]
H A DCodeGenSchedule.h147 ConstRecVec InstRWs; member
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1068 if (!SC.InstRWs.empty()) { in genSchedClassTables()
1072 for (const Record *RW : SC.InstRWs) { in genSchedClassTables()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA53.td202 // Subtarget-specific InstRWs.
H A DAArch64SchedA55.td259 // Subtarget-specific InstRWs.
H A DAArch64SchedA57.td68 // evolves, InstRWs will be used to override some of these SchedAliases.
H A DAArch64SchedA510.td241 // Subtarget-specific InstRWs.
H A DAArch64SchedA320.td238 // Subtarget-specific InstRWs.