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Searched refs:InstRWs (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.cpp939 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; in collectSchedClasses()
1070 const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs; in createInstRWClass()
1099 SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef); in createInstRWClass()
1119 for (Record *OldRWDef : SchedClasses[OldSCIdx].InstRWs) { in createInstRWClass()
1131 SC.InstRWs.push_back(OldRWDef); in createInstRWClass()
1137 SC.InstRWs.push_back(InstRWDef); in createInstRWClass()
1233 if (!SchedClasses[Idx].InstRWs.empty()) in inferSchedClasses()
1269 for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) { in inferFromInstRWs()
1270 assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!"); in inferFromInstRWs()
1271 Record *Rec = SchedClasses[SCIdx].InstRWs[I]; in inferFromInstRWs()
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H A DCodeGenSchedule.h146 RecVec InstRWs; member
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1095 if (!SC.InstRWs.empty()) { in GenSchedClassTables()
1099 for (Record *RW : SC.InstRWs) { in GenSchedClassTables()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA53.td202 // Subtarget-specific InstRWs.
H A DAArch64SchedA55.td259 // Subtarget-specific InstRWs.
H A DAArch64SchedA57.td68 // evolves, InstRWs will be used to override some of these SchedAliases.
H A DAArch64SchedA510.td241 // Subtarget-specific InstRWs.