| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | IVDescriptors.cpp | 254 InstDesc ReduxDesc(false, nullptr); in AddReductionVar()
473 InstDesc IgnoredVal(false, nullptr); in AddReductionVar()
629 RecurrenceDescriptor::InstDesc
631 Instruction *I, InstDesc &Prev) { in isAnyOfPattern()
636 return InstDesc(Select, Prev.getRecKind()); in isAnyOfPattern()
640 return InstDesc(false, I); in isAnyOfPattern()
650 return InstDesc(false, I); in isAnyOfPattern()
656 return InstDesc(false, I); in isAnyOfPattern()
658 return InstDesc(I, RecurKind::AnyOf); in isAnyOfPattern()
691 RecurrenceDescriptor::InstDesc
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | IVDescriptors.h | 105 class InstDesc {
107 InstDesc(bool IsRecur, Instruction *I, Instruction *ExactFP = nullptr)
111 InstDesc(Instruction *I, RecurKind K, Instruction *ExactFP = nullptr)
143 LLVM_ABI static InstDesc
145 InstDesc &Prev, FastMathFlags FuncFMF, ScalarEvolution *SE);
161 LLVM_ABI static InstDesc isMinMaxPattern(Instruction *I, RecurKind Kind,
162 const InstDesc &Prev);
170 LLVM_ABI static InstDesc isAnyOfPattern(Loop *Loop, PHINode *OrigPhi,
171 Instruction *I, InstDesc &Prev);
180 LLVM_ABI static InstDesc isFindIVPattern(RecurKind Kind, Loop *TheLoop,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 159 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
217 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst() argument
222 auto InstID = std::make_pair(InstDesc->getOpcode(), Subtarget); in shouldReplaceInst()
227 unsigned SCIdx = InstDesc->getSchedClass(); in shouldReplaceInst()
255 if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > ReplCost) in shouldReplaceInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 58 uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr,
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| H A D | ARMMCTargetDesc.cpp | 187 uint64_t ARM_MC::evaluateBranchTarget(const MCInstrDesc &InstDesc, in evaluateBranchTarget() argument
192 ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8; in evaluateBranchTarget()
199 if (InstDesc.getOpcode() == ARM::tBLXi) in evaluateBranchTarget()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 2789 const MCInstrDesc &InstDesc = MI.getDesc(); in isLegalToSwap() local
2790 const MCOperandInfo &OpInfo0 = InstDesc.operands()[OpIdx0]; in isLegalToSwap()
2791 const MCOperandInfo &OpInfo1 = InstDesc.operands()[OpIdx1]; in isLegalToSwap()
4501 const MCInstrDesc &InstDesc = MI.getDesc(); in isImmOperandLegal() local
4502 const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo]; in isImmOperandLegal()
4523 if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo)) in isImmOperandLegal()
6028 const MCInstrDesc &InstDesc = MI.getDesc(); in isOperandLegal() local
6029 const MCOperandInfo &OpInfo = InstDesc.operands()[OpIdx]; in isOperandLegal()
6063 usesConstantBus(MRI, Op, InstDesc.operands().begin()[i])) { in isOperandLegal()
6068 } else if (AMDGPU::isSISrcOperand(InstDesc, i) && in isOperandLegal()
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| H A D | SIFoldOperands.cpp | 2359 const MCInstrDesc &InstDesc = UseMI->getDesc(); in tryFoldRegSequence() local
2361 TII->getRegClass(InstDesc, OpIdx, TRI, *MI.getMF()); in tryFoldRegSequence()
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| H A D | GCNHazardRecognizer.cpp | 3067 const MCInstrDesc &InstDesc = I.getDesc(); in fixVALUMaskWriteHazard() local
3068 const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo]; in fixVALUMaskWriteHazard()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86AsmBackend.cpp | 342 const MCInstrDesc &InstDesc = MCII->get(Jcc.getOpcode()); in isMacroFused() local
343 if (!InstDesc.isConditionalBranch()) in isMacroFused()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2309 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode()); in addLiteralImmOperand() local
2312 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2315 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
2316 const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum); in addLiteralImmOperand()
2321 uint8_t OpTy = InstDesc.operands()[OpNum].OperandType; in addLiteralImmOperand()
2338 if (AMDGPU::isSISrcFPOperand(InstDesc, in addLiteralImmOperand()
2344 (InstDesc.getSize() != 4 || !AsmParser->has64BitLiterals()) && in addLiteralImmOperand()
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