4357   const MCInstrDesc &InstDesc = MI.getDesc();  in isImmOperandLegal()  local
4358   const MCOperandInfo &OpInfo = InstDesc.operands()[OpNo];  in isImmOperandLegal()
4379   if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))  in isImmOperandLegal()
5733   const MCInstrDesc &InstDesc = MI.getDesc();  in isOperandLegal()  local
5734   const MCOperandInfo &OpInfo = InstDesc.operands()[OpIdx];  in isOperandLegal()
5758             usesConstantBus(MRI, Op, InstDesc.operands().begin()[i])) {  in isOperandLegal()
5763       } else if (AMDGPU::isSISrcOperand(InstDesc, i) &&  in isOperandLegal()
5764                  !isInlineConstant(Op, InstDesc.operands()[i])) {  in isOperandLegal()
7787   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitUnaryOp()  local
7804   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);  in splitScalar64BitUnaryOp()
7810   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);  in splitScalar64BitUnaryOp()
8021   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitBinaryOp()  local
8050   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)  in splitScalar64BitBinaryOp()
8055   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitBinaryOp()
8128   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);  in splitScalar64BitBCNT()  local
8144   BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);  in splitScalar64BitBCNT()
8146   BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);  in splitScalar64BitBCNT()
8232   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitCountOp()  local
8253   BuildMI(MBB, MII, DL, InstDesc, MidReg1).add(SrcRegSub0);  in splitScalar64BitCountOp()
8255   BuildMI(MBB, MII, DL, InstDesc, MidReg2).add(SrcRegSub1);  in splitScalar64BitCountOp()