| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1519 bool findMatch(const BitTracker::RegisterRef &Inp,
1551 bool CopyGeneration::findMatch(const BitTracker::RegisterRef &Inp, in findMatch() argument
1553 if (!BT.has(Inp.Reg)) in findMatch()
1555 const BitTracker::RegisterCell &InpRC = BT.lookup(Inp.Reg); in findMatch()
1556 auto *FRC = HBS::getFinalVRegClass(Inp, MRI); in findMatch()
1558 if (!HBS::getSubregMask(Inp, B, W, MRI)) in findMatch()
1569 if (!HBS::isTransparentCopy(R, Inp, MRI)) in findMatch()
1592 if (HBS::isTransparentCopy(Out, Inp, MRI)) in findMatch()
2918 BitTracker::RegisterRef Inp, Out; member
3081 .addReg(G.Inp.Reg) in moveGroup()
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| H A D | HexagonISelDAGToDAGHVX.cpp | 672 ResultStack(SDNode *Inp) in ResultStack()
673 : InpNode(Inp), InpTy(Inp->getValueType(0).getSimpleVT()) {} in ResultStack()
1283 OpRef Inp[2] = {Va, Vb}; in packs() local
1355 return Inp[SrcOp]; in packs()
1387 Va = Inp[Seg0 / 2]; in packs()
1390 Results.push(Hexagon::V6_vror, Ty, {Inp[Seg0 / 2], HL}); in packs()
1512 OpRef Inp[2] = { Va, Vb }; in packp() local
1520 OpRef Op = Inp[S / 2]; in packp()
2565 SDValue Inp = N->getOperand(0); in selectExtractSubvector() local
2569 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); in selectExtractSubvector()
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| H A D | HexagonISelLoweringHVX.cpp | 2490 SDValue Inp = DAG.getBitcast(IntTy, Val); in emitHvxShiftRightRnd() local
2494 SDValue And = DAG.getNode(ISD::AND, dl, IntTy, {Inp, AmtP1}); in emitHvxShiftRightRnd()
2498 auto [Tmp0, Ovf] = emitHvxAddWithOverflow(Inp, LowBits, dl, Signed, DAG); in emitHvxShiftRightRnd()
2501 SDValue Tmp1 = DAG.getNode(ShRight, dl, IntTy, Inp, AmtM1); in emitHvxShiftRightRnd()
2716 SDValue Inp = Op.getOperand(0); in EqualizeFpIntConversion() local
2717 MVT InpTy = ty(Inp); in EqualizeFpIntConversion()
2727 SDValue WInp = resizeToWidth(Inp, WInpTy, Signed, dl, DAG); in EqualizeFpIntConversion()
2823 SDValue Inp = DAG.getBitcast(ResTy, Op0); in ExpandHvxFpToInt() local
2825 SDValue Neg = DAG.getSetCC(dl, PredTy, Inp, Zero, ISD::SETLT); in ExpandHvxFpToInt()
2829 SDValue Exp00 = DAG.getNode(ISD::SHL, dl, ResTy, {Inp, One}); in ExpandHvxFpToInt()
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| H A D | HexagonISelDAGToDAG.cpp | 709 SDValue Inp = N->getOperand(0); in SelectExtractSubvector() local
713 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); in SelectExtractSubvector()
721 SDValue Ext = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(N), ResTy, Inp); in SelectExtractSubvector()
1060 SDValue Inp = Op, Res; in SelectInlineAsmMemoryOperand() local
1068 if (SelectAddrFI(Inp, Res)) in SelectInlineAsmMemoryOperand()
1071 OutOps.push_back(Inp); in SelectInlineAsmMemoryOperand()
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| H A D | HexagonPatternsHVX.td | 951 // v31:30.h = vsxt(Inp.b) ; generate masks in odd bytes in
954 // v27.b = vadd(Inp.b,v29.b) ; x + masks
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| /freebsd/contrib/llvm-project/compiler-rt/lib/fuzzer/ |
| H A D | FuzzerDriver.cpp | 897 for (auto &Inp : *Inputs) { in FuzzerDriver()
898 Printf("Loading corpus dir: %s\n", Inp.c_str()); in FuzzerDriver()
899 ReadDirToVectorOfUnits(Inp.c_str(), &InitialCorpus, nullptr, in FuzzerDriver()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13814 SDValue Inp = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, in PerformADDVecReduce() local
13816 NA = DAG.getNode(ISD::ADD, dl, MVT::i64, Inp, NA); in PerformADDVecReduce()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 51299 SDValue Inp = Node->getOperand(i == 0 ? 1 : 0); in combineAndLoadToBZHI() local
51308 return DAG.getNode(ISD::AND, dl, VT, Inp, LShr); in combineAndLoadToBZHI()
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