| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1541 bool findMatch(const BitTracker::RegisterRef &Inp,
1573 bool CopyGeneration::findMatch(const BitTracker::RegisterRef &Inp, in findMatch() argument
1575 if (!BT.has(Inp.Reg)) in findMatch()
1577 const BitTracker::RegisterCell &InpRC = BT.lookup(Inp.Reg); in findMatch()
1578 auto *FRC = HBS::getFinalVRegClass(Inp, MRI); in findMatch()
1580 if (!HBS::getSubregMask(Inp, B, W, MRI)) in findMatch()
1591 if (!HBS::isTransparentCopy(R, Inp, MRI)) in findMatch()
1614 if (HBS::isTransparentCopy(Out, Inp, MRI)) in findMatch()
2949 BitTracker::RegisterRef Inp, Out; member
3112 .addReg(G.Inp.Reg) in moveGroup()
[all …]
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| H A D | HexagonISelDAGToDAGHVX.cpp | 64 // Inp[0] *** *** *** *** Out[0]
68 // Inp[1] *** \ / *** X *** *** Out[1]
72 // Inp[2] *** \ \ / / *** X *** *** Out[2]
76 // Inp[3] *** \ / \ / \ / *** *** *** Out[3]
82 // Inp[4] *** / \ / \ / \ *** *** *** Out[4]
86 // Inp[5] *** / / \ \ *** X *** *** Out[5]
90 // Inp[6] *** / \ *** X *** *** Out[6]
94 // Inp[7] *** *** *** *** Out[7]
677 ResultStack(SDNode *Inp) in ResultStack()
678 : InpNode(Inp), InpT in ResultStack()
1289 OpRef Inp[2] = {Va, Vb}; packs() local
1519 OpRef Inp[2] = { Va, Vb }; packp() local
2576 SDValue Inp = N->getOperand(0); selectExtractSubvector() local
2778 __anon9fc097471c02(SDValue TopShuff, SDValue Inp, MapType &&OpMap) ppHvxShuffleOfShuffle() argument
[all...] |
| H A D | HexagonISelLoweringHVX.cpp | 643 // OutV = V6_lvsplatb Inp in AdjustHvxInstrPostInstrSelection()
684 // OutV = V6_lvsplath Inp in AdjustHvxInstrPostInstrSelection()
689 // SplatV = A2_combine_ll Inp, Inp in AdjustHvxInstrPostInstrSelection()
710 // OutV = V6_lvsplatw SplatV/Inp in AdjustHvxInstrPostInstrSelection()
2453 SDValue Inp = DAG.getBitcast(IntTy, Val); in emitHvxShiftRightRnd()
2457 SDValue And = DAG.getNode(ISD::AND, dl, IntTy, {Inp, AmtP1}); in emitHvxShiftRightRnd()
2461 auto [Tmp0, Ovf] = emitHvxAddWithOverflow(Inp, LowBits, dl, Signed, DAG); in emitHvxShiftRightRnd()
2464 SDValue Tmp1 = DAG.getNode(ShRight, dl, IntTy, Inp, AmtM1); in emitHvxShiftRightRnd()
2679 SDValue Inp in EqualizeFpIntConversion()
2454 SDValue Inp = DAG.getBitcast(IntTy, Val); emitHvxShiftRightRnd() local
2680 SDValue Inp = Op.getOperand(0); EqualizeFpIntConversion() local
2787 SDValue Inp = DAG.getBitcast(ResTy, Op0); ExpandHvxFpToInt() local
3278 SDValue Inp = Op.getOperand(0); ExpandHvxResizeIntoSteps() local
[all...] |
| H A D | HexagonISelDAGToDAG.cpp | 707 SDValue Inp = N->getOperand(0); in SelectExtractSubvector() local
711 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT(); in SelectExtractSubvector()
719 SDValue Ext = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(N), ResTy, Inp); in SelectExtractSubvector()
1059 SDValue Inp = Op, Res; in SelectInlineAsmMemoryOperand() local
1067 if (SelectAddrFI(Inp, Res)) in SelectInlineAsmMemoryOperand()
1070 OutOps.push_back(Inp); in SelectInlineAsmMemoryOperand()
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| H A D | HexagonPatternsHVX.td | 936 // v31:30.h = vsxt(Inp.b) ; generate masks in odd bytes in
939 // v27.b = vadd(Inp.b,v29.b) ; x + masks
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| /freebsd/contrib/llvm-project/compiler-rt/lib/fuzzer/ |
| H A D | FuzzerDriver.cpp | 896 for (auto &Inp : *Inputs) { in FuzzerDriver()
897 Printf("Loading corpus dir: %s\n", Inp.c_str()); in FuzzerDriver()
898 ReadDirToVectorOfUnits(Inp.c_str(), &InitialCorpus, nullptr, in FuzzerDriver()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13747 SDValue Inp = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, in PerformADDVecReduce() local
13749 NA = DAG.getNode(ISD::ADD, dl, MVT::i64, Inp, NA); in PerformADDVecReduce()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 49537 SDValue Inp = (i == 0) ? Node->getOperand(1) : Node->getOperand(0); in combineAndLoadToBZHI() local
49552 return DAG.getNode(ISD::AND, dl, VT, Inp, LShr); in combineAndLoadToBZHI()
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