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Searched refs:IndexReg (Results 1 – 25 of 32) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp458 Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg(); in checkRegUsage() local
474 if (TRI->regsOverlap(Reg, IndexReg)) { in checkRegUsage()
507 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); in optLEAALU() local
510 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optLEAALU()
512 if (AluDestReg == IndexReg) { in optLEAALU()
513 if (BaseReg == IndexReg) in optLEAALU()
515 std::swap(BaseReg, IndexReg); in optLEAALU()
518 if (BaseReg == IndexReg) in optLEAALU()
532 .addReg(IndexReg, KilledIndex ? RegState::Kill : 0); in optLEAALU()
566 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
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H A DX86InstrBuilder.h53 Register IndexReg; member
71 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
102 AM.IndexReg = Op2.getReg(); in getAddressFromInstr()
180 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
H A DX86InsertPrefetch.cpp83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
87 (IndexReg == 0 || in IsMemOpCompatibleWithPrefetch()
88 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) || in IsMemOpCompatibleWithPrefetch()
89 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)); in IsMemOpCompatibleWithPrefetch()
H A DX86AsmPrinter.cpp421 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
430 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
451 assert(IndexReg.getReg() != X86::ESP && in PrintLeaMemReference()
458 if (IndexReg.getReg()) { in PrintLeaMemReference()
517 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
545 if (IndexReg.getReg()) { in PrintIntelMemReference()
560 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
H A DX86FastISel.cpp218 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
734 (AM.Base.Reg == 0 && AM.IndexReg == 0)) { in handleConstantAddresses()
753 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in handleConstantAddresses()
816 if (AM.IndexReg == 0) { in handleConstantAddresses()
818 AM.IndexReg = getRegForValue(V); in handleConstantAddresses()
819 return AM.IndexReg != 0; in handleConstantAddresses()
903 Register IndexReg = AM.IndexReg; in X86SelectAddress() local
937 if (!IndexReg && (!AM.GV || !Subtarget->isPICStyleRIPRel()) && in X86SelectAddress()
941 IndexReg = getRegForGEPIndex(PtrVT, Op); in X86SelectAddress()
942 if (!IndexReg) in X86SelectAddress()
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H A DX86ISelDAGToDAG.cpp71 SDValue IndexReg; member
93 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
124 if (IndexReg.getNode()) in dump()
125 IndexReg.getNode()->dump(DAG); in dump()
296 AM.IndexReg), 0); in getAddressOperands()
297 AM.IndexReg = Neg; in getAddressOperands()
300 if (AM.IndexReg.getNode()) in getAddressOperands()
301 Index = AM.IndexReg; in getAddressOperands()
2000 AM.Base_Reg.getNode() != nullptr && AM.IndexReg.getNode() == nullptr) { in matchAddress()
2014 AM.Base_Reg = AM.IndexReg; in matchAddress()
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H A DX86SpeculativeLoadHardening.cpp1335 Register BaseReg, IndexReg; in tracePredStateThroughBlocksAndHarden() local
1340 IndexReg = IndexMO.getReg(); in tracePredStateThroughBlocksAndHarden()
1342 if (!BaseReg && !IndexReg) in tracePredStateThroughBlocksAndHarden()
1351 (IndexReg && LoadDepRegs.test(IndexReg.id()))) in tracePredStateThroughBlocksAndHarden()
1364 !HardenedAddrRegs.count(IndexReg)) { in tracePredStateThroughBlocksAndHarden()
1375 if (IndexReg) in tracePredStateThroughBlocksAndHarden()
1376 HardenedAddrRegs.insert(IndexReg); in tracePredStateThroughBlocksAndHarden()
H A DX86MCInstLower.cpp682 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in emitNop() local
683 IndexReg = Displacement = SegmentReg = 0; in emitNop()
711 IndexReg = X86::RAX; in emitNop()
717 IndexReg = X86::RAX; in emitNop()
728 IndexReg = X86::RAX; in emitNop()
734 IndexReg = X86::RAX; in emitNop()
740 IndexReg = X86::RAX; in emitNop()
764 .addReg(IndexReg) in emitNop()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h67 MCRegister IndexReg; member
146 if (Mem.IndexReg) in print()
148 << X86IntelInstPrinter::getRegisterName(Mem.IndexReg); in print()
202 return Mem.IndexReg; in getMemIndexReg()
339 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
356 return isMem32() && X86II::isXMMReg(Mem.IndexReg); in isMem32_RC128X()
359 return isMem64() && X86II::isXMMReg(Mem.IndexReg); in isMem64_RC128X()
362 return isMem32() && X86II::isYMMReg(Mem.IndexReg); in isMem32_RC256X()
365 return isMem64() && X86II::isYMMReg(Mem.IndexReg); in isMem64_RC256X()
368 return isMem32() && X86II::isZMMReg(Mem.IndexReg); in isMem32_RC512()
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H A DX86AsmParser.cpp442 MCRegister BaseReg, IndexReg, TmpReg; member in __anonee973c6c0111::X86AsmParser::IntelExprStateMachine
478 MCRegister getIndexReg() const { return IndexReg; } in getIndexReg()
698 if (IndexReg) in onPlus()
700 IndexReg = TmpReg; in onPlus()
757 if (IndexReg) in onMinus()
759 IndexReg = TmpReg; in onMinus()
816 if (IndexReg) in onRegister()
819 IndexReg = Reg; in onRegister()
898 if (IndexReg) in onInteger()
900 IndexReg = TmpReg; in onInteger()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLoadStoreOpt.h42 Register IndexReg; variable
49 Register getIndex() { return IndexReg; } in getIndex()
50 Register getIndex() const { return IndexReg; } in getIndex()
52 void setIndex(Register NewIndex) { IndexReg = NewIndex; } in setIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp70 SDValue IndexReg; member
84 : AM(AT), BaseType(Base::RegBase), Disp(0), BaseFrameIndex(0), IndexReg(), in M68kISelAddressMode()
104 return BaseType == Base::RegBase && IndexReg.getNode() != nullptr; in hasIndexReg()
148 void setIndexReg(SDValue Reg) { IndexReg = Reg; } in setIndexReg()
161 if (IndexReg.getNode()) { in dump()
162 IndexReg.getNode()->dump(); in dump()
417 AM.IndexReg = N; in matchAddressBase()
560 AM.IndexReg = N.getOperand(1); in matchADD()
828 if (!isAddressBase(AM.BaseReg) && isAddressBase(AM.IndexReg)) { in SelectARII()
829 Base = AM.IndexReg; in SelectARII()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp181 unsigned IndexReg; member
363 return Mem.IndexReg; in getMemIndexReg()
708 Op->Mem.IndexReg = 0; in MorphToMEMri()
719 Op->Mem.IndexReg = 0; in MorphToMEMzi()
730 Op->Mem.IndexReg = Index; in MorphToMEMrri()
742 Op->Mem.IndexReg = 0; in MorphToMEMrii()
753 Op->Mem.IndexReg = Index; in MorphToMEMzri()
764 Op->Mem.IndexReg = 0; in MorphToMEMzii()
1233 MCRegister IndexReg; in parseMEMOperand() local
1237 if (parseRegister(IndexReg, S, E)) in parseMEMOperand()
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h70 StringRef IndexReg; member
78 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
84 bool hasIndexReg() const { return !IndexReg.empty(); } in hasIndexReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ATTInstPrinter.cpp451 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
461 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
468 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
473 if (IndexReg.getReg()) { in printMemReference()
H A DX86MCCodeEmitter.cpp623 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte() local
631 assert(!IndexReg.getReg() && !ForceSIB && "Invalid rip-relative address"); in emitMemModRMByte()
728 if (IndexReg.getReg()) { in emitMemModRMByte()
729 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)]; in emitMemModRMByte()
760 assert(!IndexReg.getReg() && "Unexpected index register!"); in emitMemModRMByte()
780 if (!ForceSIB && !X86II::needSIB(BaseReg, IndexReg.getReg(), in emitMemModRMByte()
839 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && in emitMemModRMByte()
876 unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4; in emitMemModRMByte()
H A DX86IntelInstPrinter.cpp393 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
408 if (IndexReg.getReg()) { in printMemReference()
422 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
H A DX86MCTargetDesc.cpp665 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress() local
668 if (SegReg.getReg() || IndexReg.getReg() || ScaleAmt.getImm() != 1 || in evaluateMemoryOperandAddress()
691 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in getMemoryOperandRelocationOffset() local
695 if (BaseReg.getReg() != X86::RIP || SegReg.getReg() || IndexReg.getReg() || in getMemoryOperandRelocationOffset()
H A DX86BaseInfo.h1324 inline bool needSIB(MCRegister BaseReg, MCRegister IndexReg, bool In64BitMode) { in needSIB() argument
1326 if (IndexReg) in needSIB()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp158 void PPCSimplifyAddress(Address &Addr, bool &UseOffset, Register &IndexReg);
408 Register &IndexReg) { in PPCSimplifyAddress() argument
428 IndexReg = PPCMaterializeInt(Offset, MVT::i64); in PPCSimplifyAddress()
429 assert(IndexReg && "Unexpected error in PPCMaterializeInt!"); in PPCSimplifyAddress()
492 Register IndexReg; in PPCEmitLoad() local
493 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitLoad()
565 if (IndexReg) in PPCEmitLoad()
566 MIB.addReg(Addr.Base.Reg).addReg(IndexReg); in PPCEmitLoad()
641 Register IndexReg; in PPCEmitStore() local
642 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitStore()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp203 unsigned IndexReg, unsigned &Offset);
2364 Register IndexReg = AArch64InstrInfo::getLdStOffsetOp(MemMI).getReg(); in mergeConstOffsetInsn() local
2370 .addDef(IndexReg) in mergeConstOffsetInsn()
2456 unsigned IndexReg, in isMatchingMovConstInsn() argument
2461 TRI->isSuperOrSubRegisterEq(IndexReg, MI.getOperand(1).getReg())) { in isMatchingMovConstInsn()
2708 Register IndexReg = AArch64InstrInfo::getLdStOffsetOp(MemMI).getReg(); in findMatchingConstOffsetBackward() local
2725 if (isMatchingMovConstInsn(*I, MI, IndexReg, Offset)) { in findMatchingConstOffsetBackward()
2734 if (!ModifiedRegUnits.available(IndexReg) || in findMatchingConstOffsetBackward()
2735 !UsedRegUnits.available(IndexReg)) in findMatchingConstOffsetBackward()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp760 Register IndexReg = MI.getOperand(2).getReg(); in legalizeBRJT() local
761 LLT IndexTy = MRI.getType(IndexReg); in legalizeBRJT()
767 IndexReg = MIRBuilder.buildShl(IndexTy, IndexReg, ShiftAmt).getReg(0); in legalizeBRJT()
769 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, PtrReg, IndexReg); in legalizeBRJT()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp359 Register IndexReg = 0; in emitInstruction() local
362 IndexReg = TargetReg; in emitInstruction()
379 .addReg(IndexReg)); in emitInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp324 uint32_t ArraySize, Register IndexReg,
3347 Register IndexReg = I.getOperand(3).getReg(); in selectResourceGetPointer() local
3356 .addUse(IndexReg) in selectResourceGetPointer()
3430 uint32_t Set, uint32_t Binding, uint32_t ArraySize, Register IndexReg, in buildPointerToResource() argument
3455 buildOpDecorate(IndexReg, MIRBuilder, SPIRV::Decoration::NonUniformEXT, {}); in buildPointerToResource()
3463 .addUse(IndexReg); in buildPointerToResource()
4131 Register IndexReg = HandleDef.getOperand(5).getReg(); in loadHandleBeforePosition() local
4147 buildPointerToResource(VarType, SC, Set, Binding, ArraySize, IndexReg, in loadHandleBeforePosition()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp303 Register IndexReg) { in buildBrJT() argument
309 .addUse(IndexReg); in buildBrJT()

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