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Searched refs:IndexReg (Results 1 – 25 of 29) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp459 Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg(); in checkRegUsage()
475 if (TRI->regsOverlap(Reg, IndexReg)) { in checkRegUsage()
508 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); in optLEAALU()
511 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optLEAALU()
513 if (AluDestReg == IndexReg) { in optLEAALU()
514 if (BaseReg == IndexReg) in optLEAALU()
516 std::swap(BaseReg, IndexReg); in optLEAALU()
519 if (BaseReg == IndexReg) in optLEAALU()
533 .addReg(IndexReg, KilledInde in optLEAALU()
458 Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg(); checkRegUsage() local
507 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); optLEAALU() local
566 Register IndexReg = Index.getReg(); optTwoAddrLEA() local
759 Register IndexReg = Index.getReg(); processInstrForSlow3OpLEA() local
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H A DX86InstrBuilder.h54 unsigned IndexReg; member
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
108 AM.IndexReg = Op2.getReg(); in getAddressFromInstr()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
H A DX86InsertPrefetch.cpp86 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
90 (IndexReg == 0 || in IsMemOpCompatibleWithPrefetch()
91 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) || in IsMemOpCompatibleWithPrefetch()
92 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)); in IsMemOpCompatibleWithPrefetch()
H A DX86AsmPrinter.cpp377 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
387 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
408 assert(IndexReg.getReg() != X86::ESP && in PrintLeaMemReference()
415 if (IndexReg.getReg()) { in PrintLeaMemReference()
474 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
504 if (IndexReg.getReg()) { in PrintIntelMemReference()
519 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
H A DX86FastISel.cpp217 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
734 (AM.Base.Reg == 0 && AM.IndexReg == 0)) { in handleConstantAddresses()
753 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in handleConstantAddresses()
816 if (AM.IndexReg == 0) { in handleConstantAddresses()
818 AM.IndexReg = getRegForValue(V); in handleConstantAddresses()
819 return AM.IndexReg != 0; in handleConstantAddresses()
903 unsigned IndexReg = AM.IndexReg; in X86SelectAddress() local
937 if (IndexReg == 0 && in X86SelectAddress()
942 IndexReg = getRegForGEPIndex(PtrVT, Op); in X86SelectAddress()
943 if (IndexReg == 0) in X86SelectAddress()
[all …]
H A DX86ISelDAGToDAG.cpp72 SDValue IndexReg; member
94 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
125 if (IndexReg.getNode()) in dump()
126 IndexReg.getNode()->dump(DAG); in dump()
285 AM.IndexReg), 0); in getAddressOperands()
286 AM.IndexReg = Neg; in getAddressOperands()
289 if (AM.IndexReg.getNode()) in getAddressOperands()
290 Index = AM.IndexReg; in getAddressOperands()
1952 AM.Base_Reg.getNode() != nullptr && AM.IndexReg.getNode() == nullptr) { in matchAddress()
1966 AM.Base_Reg = AM.IndexReg; in matchAddress()
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H A DX86SpeculativeLoadHardening.cpp1338 unsigned BaseReg = 0, IndexReg = 0; in tracePredStateThroughBlocksAndHarden() local
1343 IndexReg = IndexMO.getReg(); in tracePredStateThroughBlocksAndHarden()
1345 if (!BaseReg && !IndexReg) in tracePredStateThroughBlocksAndHarden()
1354 (IndexReg && LoadDepRegs.test(IndexReg))) in tracePredStateThroughBlocksAndHarden()
1367 !HardenedAddrRegs.count(IndexReg)) { in tracePredStateThroughBlocksAndHarden()
1378 if (IndexReg) in tracePredStateThroughBlocksAndHarden()
1379 HardenedAddrRegs.insert(IndexReg); in tracePredStateThroughBlocksAndHarden()
H A DX86MCInstLower.cpp685 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in emitNop() local
686 IndexReg = Displacement = SegmentReg = 0; in emitNop()
714 IndexReg = X86::RAX; in emitNop()
720 IndexReg = X86::RAX; in emitNop()
731 IndexReg = X86::RAX; in emitNop()
737 IndexReg = X86::RAX; in emitNop()
743 IndexReg = X86::RAX; in emitNop()
767 .addReg(IndexReg) in emitNop()
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h67 unsigned IndexReg; member
147 if (Mem.IndexReg) in print()
149 << X86IntelInstPrinter::getRegisterName(Mem.IndexReg); in print()
203 return Mem.IndexReg; in getMemIndexReg()
340 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
360 return isMem64() && X86II::isXMMReg(Mem.IndexReg); in isMem64_RC128X()
363 return isMem128() && X86II::isXMMReg(Mem.IndexReg); in isMem128_RC128X()
366 return isMem128() && X86II::isYMMReg(Mem.IndexReg); in isMem128_RC256X()
369 return isMem256() && X86II::isXMMReg(Mem.IndexReg); in isMem256_RC128X()
372 return isMem256() && X86II::isYMMReg(Mem.IndexReg); in isMem256_RC256X()
[all …]
H A DX86AsmParser.cpp437 unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0; member in __anonee973c6c0111::X86AsmParser::IntelExprStateMachine
472 unsigned getIndexReg() const { return IndexReg; } in getIndexReg()
692 if (IndexReg) in onPlus()
694 IndexReg = TmpReg; in onPlus()
751 if (IndexReg) in onMinus()
753 IndexReg = TmpReg; in onMinus()
810 if (IndexReg) in onRegister()
813 IndexReg = Reg; in onRegister()
892 if (IndexReg) in onInteger()
894 IndexReg = TmpReg; in onInteger()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp70 SDValue IndexReg; member
84 : AM(AT), BaseType(Base::RegBase), Disp(0), BaseFrameIndex(0), IndexReg(), in M68kISelAddressMode()
104 return BaseType == Base::RegBase && IndexReg.getNode() != nullptr; in hasIndexReg()
148 void setIndexReg(SDValue Reg) { IndexReg = Reg; } in setIndexReg()
161 if (IndexReg.getNode()) { in dump()
162 IndexReg.getNode()->dump(); in dump()
417 AM.IndexReg = N; in matchAddressBase()
560 AM.IndexReg = N.getOperand(1); in matchADD()
798 if (!isAddressBase(AM.BaseReg) && isAddressBase(AM.IndexReg)) { in SelectARII()
799 Base = AM.IndexReg; in SelectARII()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp185 unsigned IndexReg; member
367 return Mem.IndexReg; in getMemIndexReg()
698 Op->Mem.IndexReg = 0; in MorphToMEMri()
709 Op->Mem.IndexReg = 0; in MorphToMEMzi()
720 Op->Mem.IndexReg = Index; in MorphToMEMrri()
732 Op->Mem.IndexReg = 0; in MorphToMEMrii()
743 Op->Mem.IndexReg = Index; in MorphToMEMzri()
754 Op->Mem.IndexReg = 0; in MorphToMEMzii()
1253 MCRegister IndexReg; in parseMEMOperand() local
1257 if (parseRegister(IndexReg, S, E)) in parseMEMOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h69 StringRef IndexReg; member
77 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
83 bool hasIndexReg() const { return !IndexReg.empty(); } in hasIndexReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ATTInstPrinter.cpp427 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
437 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
444 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
449 if (IndexReg.getReg()) { in printMemReference()
H A DX86MCCodeEmitter.cpp615 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte() local
623 assert(IndexReg.getReg() == 0 && !ForceSIB && in emitMemModRMByte()
717 if (IndexReg.getReg()) { in emitMemModRMByte()
718 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)]; in emitMemModRMByte()
748 assert(IndexReg.getReg() == 0 && "Unexpected index register!"); in emitMemModRMByte()
768 if (!ForceSIB && !X86II::needSIB(BaseReg, IndexReg.getReg(), in emitMemModRMByte()
827 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && in emitMemModRMByte()
864 unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4; in emitMemModRMByte()
H A DX86IntelInstPrinter.cpp385 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
400 if (IndexReg.getReg()) { in printMemReference()
414 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
H A DX86MCTargetDesc.cpp666 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress() local
669 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || in evaluateMemoryOperandAddress()
692 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in getMemoryOperandRelocationOffset() local
697 IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || !Disp.isImm()) in getMemoryOperandRelocationOffset()
H A DX86BaseInfo.h1321 inline bool needSIB(unsigned BaseReg, unsigned IndexReg, bool In64BitMode) { in needSIB() argument
1323 if (IndexReg) in needSIB()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp166 unsigned &IndexReg);
420 unsigned &IndexReg) { in PPCSimplifyAddress() argument
440 IndexReg = PPCMaterializeInt(Offset, MVT::i64); in PPCSimplifyAddress()
441 assert(IndexReg && "Unexpected error in PPCMaterializeInt!"); in PPCSimplifyAddress()
504 unsigned IndexReg = 0; in PPCEmitLoad() local
505 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitLoad()
577 if (IndexReg) in PPCEmitLoad()
578 MIB.addReg(Addr.Base.Reg).addReg(IndexReg); in PPCEmitLoad()
653 unsigned IndexReg = 0; in PPCEmitStore() local
654 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitStore()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLoadStoreOpt.h41 Register IndexReg;
48 Register getIndex() { return IndexReg; }
49 Register getIndex() const { return IndexReg; }
51 void setIndex(Register NewIndex) { IndexReg = NewIndex; }
39 Register IndexReg; global() member
H A DMachineIRBuilder.h848 Register IndexReg);
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp340 Register IndexReg = 0; in emitInstruction() local
343 IndexReg = TargetReg; in emitInstruction()
359 .addReg(IndexReg)); in emitInstruction()
H A DSystemZISelLowering.cpp991 bool IndexReg; member
994 LongDisplacement(LongDispl), IndexReg(IdxReg) {} in AddressingMode()
1102 if (!SupportedAM.IndexReg) in isLegalAddressingMode()
8408 Register IndexReg = MI.getOperand(3).getReg(); in emitCondStore() local
8427 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) { in emitCondStore()
8476 .addReg(IndexReg) in emitCondStore()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp303 Register IndexReg) { in buildBrJT() argument
309 .addUse(IndexReg); in buildBrJT()

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