437     unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0;  member in __anonee973c6c0111::X86AsmParser::IntelExprStateMachine
472     unsigned getIndexReg() const { return IndexReg; }  in getIndexReg()
692             if (IndexReg)  in onPlus()
694             IndexReg = TmpReg;  in onPlus()
751             if (IndexReg)  in onMinus()
753             IndexReg = TmpReg;  in onMinus()
810           if (IndexReg)  in onRegister()
813           IndexReg = Reg;  in onRegister()
892           if (IndexReg)  in onInteger()
894           IndexReg = TmpReg;  in onInteger()
996             if (IndexReg)  in onRBrac()
998             IndexReg = TmpReg;  in onRBrac()
1155                                unsigned BaseReg, unsigned IndexReg,
1303 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
1319   if (IndexReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1320       !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||  in CheckBaseRegAndIndexRegAndScale()
1321         X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1322         X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1323         X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1324         X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1325         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1326         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {  in CheckBaseRegAndIndexRegAndScale()
1331   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1332       IndexReg == X86::EIP || IndexReg == X86::RIP ||  in CheckBaseRegAndIndexRegAndScale()
1333       IndexReg == X86::ESP || IndexReg == X86::RSP) {  in CheckBaseRegAndIndexRegAndScale()
1348       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1353   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1355         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1356          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1357          IndexReg == X86::EIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1362         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1363          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1364          IndexReg == X86::RIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1369       if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1370           X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1375           (IndexReg != X86::SI && IndexReg != X86::DI)) {  in CheckBaseRegAndIndexRegAndScale()
1757                                            unsigned BaseReg, unsigned IndexReg,  in CreateMemForMSInlineAsm()  argument
1788     if (BaseReg || IndexReg) {  in CreateMemForMSInlineAsm()
1791                                                BaseReg && IndexReg));  in CreateMemForMSInlineAsm()
1798       getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,  in CreateMemForMSInlineAsm()
2655   unsigned IndexReg = SM.getIndexReg();  in parseIntelOperand()  local
2656   if (IndexReg && BaseReg == X86::RIP)  in parseIntelOperand()
2663       (IndexReg == X86::ESP || IndexReg == X86::RSP))  in parseIntelOperand()
2664     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2669       !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in parseIntelOperand()
2670         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in parseIntelOperand()
2671         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&  in parseIntelOperand()
2675     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2678       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))  in parseIntelOperand()
2689       (IndexReg == X86::BX || IndexReg == X86::BP))  in parseIntelOperand()
2690     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2692   if ((BaseReg || IndexReg) &&  in parseIntelOperand()
2693       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in parseIntelOperand()
2699     return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale,  in parseIntelOperand()
2711         ((PtrInOperand && !IndexReg) || SM.getElementSize() > 0)) {  in parseIntelOperand()
2719       } else if (!BaseReg && !IndexReg && Disp &&  in parseIntelOperand()
2741   if ((BaseReg || IndexReg || RegNo || DefaultBaseReg != X86::NoRegister))  in parseIntelOperand()
2743         getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End,  in parseIntelOperand()
3044   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
3083         IndexReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
3088         if (IndexReg == X86::RIP)  in ParseMemOperand()
3121   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
3128   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
3137   if (BaseReg || IndexReg) {  in ParseMemOperand()
3141                   X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg);  in ParseMemOperand()
3161   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
3163                                              BaseReg, IndexReg, Scale, StartLoc,  in ParseMemOperand()