Searched refs:InLo (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1591 auto [InLo, InHi] = DAG.SplitVectorOperand(N, 0); in SplitVecRes_BITCAST()
1592 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, InLo); in SplitVecRes_BITCAST()
1800 SDValue InLo, InHi; in SplitVecRes_ExtVecInRegOp() local
1803 GetSplitVector(N0, InLo, InHi); in SplitVecRes_ExtVecInRegOp()
1805 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_ExtVecInRegOp()
1807 EVT InLoVT = InLo.getValueType(); in SplitVecRes_ExtVecInRegOp()
1826 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi); in SplitVecRes_ExtVecInRegOp()
1828 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo); in SplitVecRes_ExtVecInRegOp()
3154 SDValue InLo, InHi; in SplitVecRes_VECTOR_REVERSE() local
3155 GetSplitVector(N->getOperand(0), InLo, InHi); in SplitVecRes_VECTOR_REVERSE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1406 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1}); in insertHvxSubvectorReg() local
1408 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo); in insertHvxSubvectorReg()
1453 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SingleV, V1}); in insertHvxSubvectorReg() local
1455 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo); in insertHvxSubvectorReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 1329 SDValue InLo, InHi; in initAccumulator() local
1330 std::tie(InLo, InHi) = DAG.SplitScalar(In, DL, MVT::i32, MVT::i32); in initAccumulator()
1331 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); in initAccumulator()
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