Searched refs:InHi (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1523 auto [InLo, InHi] = DAG.SplitVectorOperand(N, 0); in SplitVecRes_BITCAST()
1525 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, InHi); in SplitVecRes_BITCAST()
1723 SDValue InLo, InHi; in SplitVecRes_ExtVecInRegOp()
1726 GetSplitVector(N0, InLo, InHi); in SplitVecRes_ExtVecInRegOp()
1728 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_ExtVecInRegOp()
1745 // create a 'fake' InHi. in SplitVecRes_ExtVecInRegOp()
1749 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi); in SplitVecRes_ExtVecInRegOp()
1752 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi); in SplitVecRes_StrictFPOp()
3019 SDValue InLo, InHi; in SplitVecRes_VECTOR_REVERSE()
3020 GetSplitVector(N->getOperand(0), InLo, InHi); in SplitVecRes_VECTOR_REVERSE()
1719 SDValue InLo, InHi; SplitVecRes_ExtVecInRegOp() local
3015 SDValue InLo, InHi; SplitVecRes_VECTOR_REVERSE() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1392 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV}); in insertHvxSubvectorReg()
1393 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo); in insertHvxSubvectorReg() local
1439 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SingleV}); in insertHvxSubvectorReg()
1440 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo); in insertHvxSubvectorReg() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 1285 SDValue InLo, InHi; in initAccumulator() local
1286 std::tie(InLo, InHi) = DAG.SplitScalar(In, DL, MVT::i32, MVT::i32); in initAccumulator()
1287 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); in initAccumulator()
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