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Searched refs:In64BitMode (Results 1 – 25 of 32) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSNP.td21 Requires<[In64BitMode]>;
26 TB, XD, Requires<[In64BitMode]>;
35 Requires<[In64BitMode]>;
40 Requires<[In64BitMode]>;
45 Requires<[In64BitMode]>;
48 def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>;
49 def : InstAlias<"pvalidate\t{%rax, %rcx, %rdx|rdx, rcx, rax|}", (PVALIDATE64)>, Requires<[In64BitMode]>;
51 def : InstAlias<"rmpupdate\t{%rax, %rcx|rcx, rax|}", (RMPUPDATE)>, Requires<[In64BitMode]>;
52 def : InstAlias<"rmpadjust\t{%rax, %rcx, %rdx|rdx, rcx, rax|}", (RMPADJUST)>, Requires<[In64BitMode]>;
53 def : InstAlias<"rmpquery\t{%rax, %rdx|rdx, rax|}", (RMPQUERY)>, Requires<[In64BitMode]>;
[all...]
H A DX86InstrVMX.td24 Requires<[In64BitMode]>;
27 EVEX, NoCD8, T_MAP4, XS, WIG, Requires<[In64BitMode]>;
35 Requires<[In64BitMode]>;
38 EVEX, NoCD8, T_MAP4, XS, WIG, Requires<[In64BitMode]>;
58 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
64 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
70 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
76 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
H A DX86InstrControl.td26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
38 "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
44 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
54 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
105 "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>;
125 [(brind GR64:$dst)]>, Requires<[In64BitMode]>,
128 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>,
162 [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>,
166 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK;
[all …]
H A DX86InstrSVM.td37 Requires<[In64BitMode]>;
45 Requires<[In64BitMode]>;
53 Requires<[In64BitMode]>;
61 "invlpga", []>, TB, Requires<[In64BitMode]>;
H A DX86InstrSystem.td64 Requires<[In64BitMode]>;
70 Requires<[In64BitMode]>;
75 []>, TB, XD, Requires<[In64BitMode]>;
77 []>, TB, XS, Requires<[In64BitMode]>;
139 Requires<[In64BitMode]>;
146 Requires<[In64BitMode]>;
158 Requires<[In64BitMode]>;
165 Requires<[In64BitMode]>;
188 Requires<[In64BitMode]>;
227 []>, TB, XD, Requires<[In64BitMode]>;
[all …]
H A DX86InstrArithmetic.td32 OpSize32, Requires<[In64BitMode]>;
91 def 64m : MulDivOpM<o, MemMRM, m, Xi64, WriteIMul64, []>, Requires<[In64BitMode]>;
93 let Predicates = [In64BitMode] in {
153 def 64m : MulDivOpM<o, MemMRM, m, Xi64, sched64, []>, Requires<[In64BitMode]>;
155 let Predicates = [In64BitMode] in {
230 let Predicates = [HasNDD, In64BitMode] in {
239 let Predicates = [In64BitMode], Pattern = [(null_frag)] in {
310 let Predicates = [In64BitMode] in {
360 let Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in {
427 let Predicates = [HasNDD, In64BitMode] in {
[all …]
H A DX86InstrAsmAlias.td36 Requires<[ In64BitMode ]>;
42 Requires<[ In64BitMode ]>;
46 def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
50 def : InstAlias<"invlpgb\t{%rax, %edx|rax, edx}", (INVLPGB64)>, Requires<[In64BitMode]>;
54 let Predicates = [In64BitMode] in {
69 let Predicates = [In64BitMode] in {
143 let Predicates = [In64BitMode] in {
225 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
239 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
246 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
[all …]
H A DX86InstrCMovSetCC.td33 let Predicates = [HasCMOV, HasCF, In64BitMode] in {
44 let Predicates = [HasCMOV, HasCF, HasNDD, In64BitMode] in
50 let Predicates = [HasCMOV, HasCF, In64BitMode], mayLoad = 1 in
54 let Predicates = [HasCMOV, HasCF, HasNDD, In64BitMode], mayLoad = 1 in
60 Predicates = [HasCMOV, HasCF, In64BitMode], mayStore = 1 in
73 let Predicates = [HasCMOV, HasNDD, In64BitMode] in {
153 hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [HasNDD] in {
H A DX86InstrMisc.td25 "nop{q}\t$zero", []>, TB, Requires<[In64BitMode]>;
32 "nop{q}\t$zero", []>, TB, Requires<[In64BitMode]>;
47 Requires<[In64BitMode]>;
125 Requires<[In64BitMode]>;
138 Requires<[In64BitMode]>;
158 OpSize32, Requires<[In64BitMode]>;
162 OpSize32, Requires<[In64BitMode]>;
165 REX_W, ExplicitREX2Prefix, Requires<[In64BitMode]>;
176 OpSize32, Requires<[In64BitMode]>;
179 OpSize32, Requires<[In64BitMode]>;
[all …]
H A DX86InstrExtension.td22 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
34 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
158 Sched<[WriteALU]>, Requires<[In64BitMode]>;
162 Sched<[WriteLoad]>, Requires<[In64BitMode]>;
170 Sched<[WriteALU]>, OpSize16, Requires<[In64BitMode]>;
173 Sched<[WriteALU]>, OpSize32, Requires<[In64BitMode]>;
177 Sched<[WriteLoad]>, OpSize16, Requires<[In64BitMode]>;
180 Sched<[WriteLoad]>, OpSize32, Requires<[In64BitMode]>;
H A DX86InstrAMX.td18 let Predicates = [HasAMXTILE, HasEGPR, In64BitMode] in {
52 let Predicates = [HasAMXTILE, In64BitMode] in {
98 let Predicates = [HasAMXINT8, In64BitMode] in {
170 let Predicates = [HasAMXBF16, In64BitMode] in {
200 let Predicates = [HasAMXFP16, In64BitMode] in {
229 let Predicates = [HasAMXCOMPLEX, In64BitMode] in {
H A DX86InstrShiftRotate.td29 let Predicates = [HasNDD, In64BitMode] in {
35 let Predicates = [In64BitMode] in {
46 def 64mi : BinOpMI8U_M<m, MemMRM, Xi64, node>, Sched<[mi, WriteRMW]>, DefEFLAGS, Requires<[In64BitMode]>;
47 let Predicates = [HasNDD, In64BitMode] in {
53 let Predicates = [In64BitMode] in {
72 let Predicates = [In64BitMode] in {
89 def 64m1 : UnaryOpM_MF<0xD1, MemMRM, m, Xi64>, Requires<[In64BitMode]>;
91 let Predicates = [In64BitMode] in {
98 let SchedRW = [mi, ri], Predicates = [In64BitMode] in {
113 let Predicates = [HasNDD, In64BitMode] i
[all...]
H A DX86InstrTDX.td18 let SchedRW = [WriteSystem], Predicates = [In64BitMode] in {
H A DX86InstrCompiler.td91 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>;
98 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>;
118 Requires<[In64BitMode]>;
135 Requires<[In64BitMode]>;
161 Requires<[In64BitMode]>;
173 Requires<[In64BitMode]>, Sched<[WriteALU]>;
217 Requires<[In64BitMode]>;
226 Requires<[In64BitMode]>;
387 Requires<[NotLP64, In64BitMode]>;
430 Requires<[NotLP64, In64BitMode]>;
[all …]
H A DX86InstrRAOINT.td42 let Predicates = [HasRAOINT, HasEGPR, In64BitMode] in {
H A DX86MCInstLower.cpp412 bool In64BitMode = AsmPrinter.getSubtarget().is64Bit(); in Lower() local
416 X86::optimizeMOVSX(OutMI) || X86::optimizeINCDEC(OutMI, In64BitMode) || in Lower()
417 X86::optimizeMOV(OutMI, In64BitMode) || in Lower()
475 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX; in Lower()
505 if (In64BitMode) in Lower()
H A DX86InstrConditionalCompare.td15 … m#"${cond}", "$dcf\t{$src2, $src1|$src1, $src2}" , []>, T_MAP4, EVEX, Requires<[In64BitMode]> {
H A DX86InstrPredicates.td189 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
H A DX86InstrFPStack.td673 TB, Requires<[HasFXSR, In64BitMode]>;
682 TB, Requires<[HasFXSR, In64BitMode]>;
H A DX86InstrMMX.td554 let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86EncodingOptimization.h23 bool optimizeINCDEC(MCInst &MI, bool In64BitMode);
24 bool optimizeMOV(MCInst &MI, bool In64BitMode);
H A DX86EncodingOptimization.cpp311 bool X86::optimizeINCDEC(MCInst &MI, bool In64BitMode) { in optimizeINCDEC() argument
312 if (In64BitMode) in optimizeINCDEC()
337 bool X86::optimizeMOV(MCInst &MI, bool In64BitMode) { in optimizeMOV() argument
340 if (In64BitMode) in optimizeMOV()
H A DX86BaseInfo.h1321 inline bool needSIB(unsigned BaseReg, unsigned IndexReg, bool In64BitMode) { in needSIB() argument
1333 return In64BitMode && !BaseReg; in needSIB()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td79 [(PPCretglue)]>, Requires<[In64BitMode]>;
84 Requires<[In64BitMode]>;
88 Requires<[In64BitMode]>;
92 Requires<[In64BitMode]>;
95 Requires<[In64BitMode]>;
163 Requires<[In64BitMode]>;
169 Requires<[In64BitMode]>;
173 Requires<[In64BitMode]>;
176 Requires<[In64BitMode]>;
210 Requires<[In64BitMode]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrFPU.td105 // S64 - single precision in 32 64bit fp registers (In64BitMode)
107 // D64 - double precision in 32 64bit fp registers (In64BitMode)

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