| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6qdl-dhcom-picoitx.dtsi | 29 "", "", "DHCOM-A", "", "DHCOM-B", "PicoITX-In2", "", "",
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| H A D | imx6ull-dhcom-picoitx.dts | 76 "DHCOM-A", "DHCOM-B", "PicoITX-In2", "PicoITX-Out2",
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| H A D | imx6ull-dhcom-drc02.dts | 35 "", "", "", "DRC02-In2",
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| H A D | imx6qdl-dhcom-drc02.dtsi | 48 "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H",
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| H A D | imx6dl-eckelmann-ci4x10.dts | 149 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stm32mp15xx-dhcom-picoitx.dtsi | 63 gpio-line-names = "PicoITX-In2", "", "", "",
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| H A D | stm32mp15xx-dhcom-drc02.dtsi | 42 "DRC02-In2", "", "", "",
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8mp-dhcom-picoitx.dts | 93 "", "", "PicoITX-In2", "", "", "", "", "",
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| H A D | imx8mp-dhcom-drc02.dts | 96 "", "", "", "", "DRC02-In2", "", "", "",
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 42 static bool addWithOverflow(APInt &Result, const APInt &In1, const APInt &In2, in addWithOverflow() argument
46 Result = In1.sadd_ov(In2, Overflow); in addWithOverflow()
48 Result = In1.uadd_ov(In2, Overflow); in addWithOverflow()
55 static bool subWithOverflow(APInt &Result, const APInt &In1, const APInt &In2, in subWithOverflow() argument
59 Result = In1.ssub_ov(In2, Overflow); in subWithOverflow()
61 Result = In1.usub_ov(In2, Overflow); in subWithOverflow()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 5429 SDValue In1, In2, In3, In4; in ExpandIntRes_FunnelShift() local
5431 GetExpandedInteger(N->getOperand(1), In1, In2); in ExpandIntRes_FunnelShift()
5452 SDValue Select1 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In1, In2); in ExpandIntRes_FunnelShift()
5453 SDValue Select2 = DAG.getNode(ISD::SELECT, DL, HalfVT, Cond, In2, In3); in ExpandIntRes_FunnelShift()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2378 SDValue In2 = Op.getOperand(1); in LowerFCOPYSIGN() local
2379 EVT SrcVT = In2.getValueType(); in LowerFCOPYSIGN()
2384 return DAG.getNode(NVPTXISD::FCOPYSIGN, DL, VT, In1, In2); in LowerFCOPYSIGN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10593 SDValue In2 = Op.getOperand(1); in LowerFCOPYSIGN() local
10594 EVT SrcVT = In2.getValueType(); in LowerFCOPYSIGN()
10597 In2 = DAG.getFPExtendOrRound(In2, DL, VT); in LowerFCOPYSIGN()
10608 In2 = convertToScalableVector(DAG, ContainerVT, In2); in LowerFCOPYSIGN()
10610 SDValue Res = DAG.getNode(ISD::FCOPYSIGN, DL, ContainerVT, In1, In2); in LowerFCOPYSIGN()
10626 DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, SVT, DAG.getUNDEF(SVT), In2, in LowerFCOPYSIGN()
10647 DAG.getTargetInsertSubreg(Idx, DL, VecVT, DAG.getUNDEF(VecVT), In2); in LowerFCOPYSIGN()
10650 VecVal2 = BitCast(VecVT, In2, DAG); in LowerFCOPYSIGN()
26440 SDValue In2 = N->getOperand(2); in performBSPExpandForSVE() local
26444 SDValue SelInv = DAG.getNode(ISD::AND, DL, VT, InvMask, In2); in performBSPExpandForSVE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 20090 SDValue In2 = N->getOperand(1); in PerformDAGCombine() local
20093 if (!In2.hasOneUse()) in PerformDAGCombine()
20095 if (In2.getOpcode() != ISD::FP_EXTEND && in PerformDAGCombine()
20096 (In2.getOpcode() != ISD::FP_ROUND || In2.getConstantOperandVal(1) != 0)) in PerformDAGCombine()
20098 In2 = In2.getOperand(0); in PerformDAGCombine()
20099 if (In2.getOpcode() != ISD::FNEG) in PerformDAGCombine()
20102 SDValue NewFPExtRound = DAG.getFPExtendOrRound(In2.getOperand(0), DL, VT); in PerformDAGCombine()
|