Home
last modified time | relevance | path

Searched refs:ImmType (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFormats.td83 // ImmType - This specifies the immediate type used by an instruction. This is
86 class ImmType<bits<4> val> {
89 def NoImm : ImmType<0>;
90 def Imm8 : ImmType<1>;
91 def Imm8PCRel : ImmType<2>;
92 def Imm8Reg : ImmType<3>; // Register encoded in [7:4].
93 def Imm16 : ImmType<4>;
94 def Imm16PCRel : ImmType<5>;
95 def Imm32 : ImmType<6>;
96 def Imm32PCRel : ImmType<7>;
[all …]
H A DX86InstrUtils.td69 ImmType ImmT = Imm8;
73 ImmType ImmT = Imm8;
77 ImmType ImmT = Imm8;
81 ImmType ImmT = Imm8;
85 ImmType ImmT = Imm8;
133 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
161 ImmType ImmEncoding = immkind;
814 ImmType ImmT = Imm8;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td79 class I_16_ZX<string op, ImmLeaf ImmType, list<dag> pattern>
81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
93 class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
94 : CSKY32Inst<AddrModeNone, 0x3a, (outs GPR:$rz), (ins ImmType:$imm16),
96 [(set GPR:$rz, ImmType:$imm16)]> {
197 class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
199 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
200 [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
264 class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
267 (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFastISel.h377 MVT ImmType);
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td2045 ValueType regT, NVPTXRegClass regclass, Operand ImmType,
2063 (ins Int16Regs:$src, ImmType:$b),
2066 (ins Int32Regs:$src, ImmType:$b),
2069 (ins Int64Regs:$src, ImmType:$b),
2075 Operand ImmType, SDNode Imm, ValueType ImmTy,
2088 (ins Int32Regs:$src, ImmType:$b, regclass:$c),
2091 (ins Int64Regs:$src, ImmType:$b, regclass:$c),
2094 (ins Int32Regs:$src, regclass:$b, ImmType:$c),
2097 (ins Int64Regs:$src, regclass:$b, ImmType:$c),
2101 (ins Int32Regs:$src, ImmType:$b, ImmType:$c),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td2275 multiclass VPseudoBinaryV_VI<Operand ImmType, LMULInfo m, string Constraint = ""> {
2276 defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
2279 multiclass VPseudoBinaryV_VI_RM<Operand ImmType, LMULInfo m, string Constraint = ""> {
2280 defm _VI : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m, Constraint>;
2317 multiclass VPseudoBinaryW_VI<Operand ImmType, LMULInfo m> {
2318 defm "_VI" : VPseudoBinary<m.wvrclass, m.vrclass, ImmType, m,
5410 list<VTypeInfo> vtilist, Operand ImmType = simm5>
5413 VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
5416 list<VTypeInfo> vtilist, Operand ImmType>
5419 VPatBinaryV_VI_RM<intrinsic, instruction, vtilist, ImmType>;
[all...]
H A DRISCVInstrInfoVSDPatterns.td160 Operand ImmType = simm5>
167 !cast<ComplexPattern>(SplatPat#_#ImmType),
168 ImmType>;
H A DRISCVInstrInfo.td1195 class PatGprImm<SDPatternOperator OpNode, RVInst Inst, ImmLeaf ImmType,
1197 : Pat<(vt (OpNode (vt GPR:$rs1), ImmType:$imm)),
1198 (Inst GPR:$rs1, ImmType:$imm)>;
H A DRISCVInstrInfoVVLPatterns.td888 Operand ImmType = simm5>
895 !cast<ComplexPattern>(SplatPat#_#ImmType),
896 ImmType>;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1986 uint64_t Imm, MVT ImmType) { in fastEmit_ri_() argument
2007 Register MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm); in fastEmit_ri_()