| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreEmitPeephole.cpp | 250 Register IdxReg = Idx->isReg() ? Idx->getReg() : Register(); in optimizeSetGPR() local
273 if (IdxReg && I->modifiesRegister(IdxReg, TRI)) in optimizeSetGPR()
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| H A D | AMDGPUInstructionSelector.cpp | 3012 const TargetRegisterClass *SuperRC, Register IdxReg, in computeIndirectRegIndex() argument
3018 AMDGPU::getBaseWithConstantOffset(MRI, IdxReg, &KnownBits); in computeIndirectRegIndex()
3023 IdxBaseReg = IdxReg; in computeIndirectRegIndex()
3031 return std::pair(IdxReg, SubRegs[0]); in computeIndirectRegIndex()
3039 Register IdxReg = MI.getOperand(2).getReg(); in selectG_EXTRACT_VECTOR_ELT() local
3046 const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI); in selectG_EXTRACT_VECTOR_ELT()
3061 !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI)) in selectG_EXTRACT_VECTOR_ELT()
3069 std::tie(IdxReg, SubReg) = computeIndirectRegIndex( in selectG_EXTRACT_VECTOR_ELT()
3070 *MRI, TRI, SrcRC, IdxReg, DstTy.getSizeInBits() / 8, *KB); in selectG_EXTRACT_VECTOR_ELT()
3077 .addReg(IdxReg); in selectG_EXTRACT_VECTOR_ELT()
[all …]
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| H A D | AMDGPURegisterBankInfo.cpp | 4632 Register IdxReg = MI.getOperand(3).getReg(); in getInstrMapping() local
4633 unsigned IdxSize = MRI.getType(IdxReg).getSizeInBits(); in getInstrMapping()
4634 unsigned IdxBank = getRegBankID(IdxReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4650 Register IdxReg = MI.getOperand(3).getReg(); in getInstrMapping() local
4651 unsigned IdxSize = MRI.getType(IdxReg).getSizeInBits(); in getInstrMapping()
4652 unsigned IdxBank = getRegBankID(IdxReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMConstantIslandPass.cpp | 2274 unsigned IdxReg = ~0U; in optimizeThumb2JumpTables() local
2277 IdxReg = MI->getOperand(1).getReg(); in optimizeThumb2JumpTables()
2301 IdxReg = Shift->getOperand(2).getReg(); in optimizeThumb2JumpTables()
2307 if (BaseReg == IdxReg && !jumpTableFollowsTB(MI, User.CPEMI)) in optimizeThumb2JumpTables()
2338 if (registerDefinedBetween(IdxReg, Add->getNextNode(), MI, TRI)) in optimizeThumb2JumpTables()
2346 if (registerDefinedBetween(IdxReg, Load->getNextNode(), MI, TRI)) in optimizeThumb2JumpTables()
2369 .addReg(IdxReg, getKillRegState(IdxRegKill)) in optimizeThumb2JumpTables()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 1640 Register IdxReg = getOrCreateVReg(*Idx); in translateGetElementPtr() local
1641 LLT IdxTy = MRI->getType(IdxReg); in translateGetElementPtr()
1644 IdxReg = MIRBuilder in translateGetElementPtr()
1646 IdxReg) in translateGetElementPtr()
1650 IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0); in translateGetElementPtr()
1660 MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0); in translateGetElementPtr()
1662 GepOffsetReg = IdxReg; in translateGetElementPtr()
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| H A D | LegalizerHelper.cpp | 4141 static Register clampVectorIndex(MachineIRBuilder &B, Register IdxReg, in clampVectorIndex() argument
4143 LLT IdxTy = B.getMRI()->getType(IdxReg); in clampVectorIndex()
4147 if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal))) { in clampVectorIndex()
4149 return IdxReg; in clampVectorIndex()
4155 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); in clampVectorIndex()
4158 return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1)) in clampVectorIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 6864 Register IdxReg = I.getOperand(2 + NumVec + isExt).getReg(); in SelectTable() local
6868 Instr = MIB.buildInstr(Opc, {DstReg}, {Reg, RegSeq, IdxReg}); in SelectTable()
6870 Instr = MIB.buildInstr(Opc, {DstReg}, {RegSeq, IdxReg}); in SelectTable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 993 AddressingMode(bool LongDispl, bool IdxReg) : in AddressingMode()
994 LongDisplacement(LongDispl), IndexReg(IdxReg) {} in AddressingMode()
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