3012                         const TargetRegisterClass *SuperRC, Register IdxReg,  in computeIndirectRegIndex()  argument
3018       AMDGPU::getBaseWithConstantOffset(MRI, IdxReg, &KnownBits);  in computeIndirectRegIndex()
3023     IdxBaseReg = IdxReg;  in computeIndirectRegIndex()
3031     return std::pair(IdxReg, SubRegs[0]);  in computeIndirectRegIndex()
3039   Register IdxReg = MI.getOperand(2).getReg();  in selectG_EXTRACT_VECTOR_ELT()  local
3046   const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI);  in selectG_EXTRACT_VECTOR_ELT()
3061       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))  in selectG_EXTRACT_VECTOR_ELT()
3069   std::tie(IdxReg, SubReg) = computeIndirectRegIndex(  in selectG_EXTRACT_VECTOR_ELT()
3070       *MRI, TRI, SrcRC, IdxReg, DstTy.getSizeInBits() / 8, *KB);  in selectG_EXTRACT_VECTOR_ELT()
3077       .addReg(IdxReg);  in selectG_EXTRACT_VECTOR_ELT()
3092       .addReg(IdxReg);  in selectG_EXTRACT_VECTOR_ELT()
3104       .addReg(IdxReg)  in selectG_EXTRACT_VECTOR_ELT()
3117   Register IdxReg = MI.getOperand(3).getReg();  in selectG_INSERT_VECTOR_ELT()  local
3126   const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI);  in selectG_INSERT_VECTOR_ELT()
3143       !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI))  in selectG_INSERT_VECTOR_ELT()
3150   std::tie(IdxReg, SubReg) =  in selectG_INSERT_VECTOR_ELT()
3151       computeIndirectRegIndex(*MRI, TRI, VecRC, IdxReg, ValSize / 8, *KB);  in selectG_INSERT_VECTOR_ELT()
3161       .addReg(IdxReg);  in selectG_INSERT_VECTOR_ELT()
3178       .addReg(IdxReg)  in selectG_INSERT_VECTOR_ELT()
3235     Register IdxReg = MRI->createVirtualRegister(TRI.getVGPR64Class());  in selectBufferLoadLds()  local
3236     BuildMI(*MBB, &*MIB, DL, TII.get(AMDGPU::REG_SEQUENCE), IdxReg)  in selectBufferLoadLds()
3242     MIB.addReg(IdxReg);  in selectBufferLoadLds()