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Searched refs:Idx1 (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuilder.h64 Address createConstGEP2_32(Address Addr, unsigned Idx0, unsigned Idx1, in createConstGEP2_32() argument
71 Idx1, Name); in createConstGEP2_32()
74 emitRawPointerFromAddress(Addr), Idx0, Idx1, Name); in createConstGEP2_32()
79 Addr.getElementType(), {getInt32(Idx0), getInt32(Idx1)}, DL, in createConstGEP2_32()
84 Addr.getElementType(), {Idx0, Idx1}); in createConstGEP2_32()
329 Address CreateConstInBoundsGEP2_32(Address Addr, unsigned Idx0, unsigned Idx1,
331 return createConstGEP2_32<true>(Addr, Idx0, Idx1, Name);
335 Address CreateConstGEP2_32(Address Addr, unsigned Idx0, unsigned Idx1,
337 return createConstGEP2_32<false>(Addr, Idx0, Idx1, Name);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp183 bool NewMI, unsigned Idx1, in commuteInstructionImpl() argument
191 unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1; in commuteInstructionImpl()
194 CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 && in commuteInstructionImpl()
196 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() && in commuteInstructionImpl()
200 Register Reg1 = MI.getOperand(Idx1).getReg(); in commuteInstructionImpl()
203 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl()
205 bool Reg1IsKill = MI.getOperand(Idx1).isKill(); in commuteInstructionImpl()
207 bool Reg1IsUndef = MI.getOperand(Idx1).isUndef(); in commuteInstructionImpl()
209 bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead(); in commuteInstructionImpl()
214 Reg1.isPhysical() ? MI.getOperand(Idx1).isRenamable() : false; in commuteInstructionImpl()
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H A DShadowStackGCLowering.cpp80 Type *Ty, Value *BasePtr, int Idx1,
83 Type *Ty, Value *BasePtr, int Idx1, int Idx2,
H A DPeepholeOptimizer.cpp594 RecurrenceInstr(MachineInstr *MI, unsigned Idx1, unsigned Idx2) in RecurrenceInstr() argument
595 : MI(MI), CommutePair(std::make_pair(Idx1, Idx2)) {} in RecurrenceInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td1267 foreach Idx1 = 1...4 in {
1268 defvar CImm = !add(1, !shl(!add(1, !shl(1, Idx0)), Idx1));
1271 GPR:$r, (i32 Idx1))>;
1275 foreach Idx1 = 1...4 in {
1277 defvar CImm = !add(Cb, !shl(Cb, Idx1));
1280 (ALSL_W GPR:$r, GPR:$r, (i32 Idx0)), (i32 Idx1))>;
1287 foreach Idx1 = 1...4 in {
1288 defvar CImm = !add(1, !shl(!add(1, !shl(1, Idx0)), Idx1));
1291 GPR:$r, (i64 Idx1))>;
1294 GPR:$r, (i64 Idx1))>;
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIRBuilder.h1961 Value *CreateConstGEP2_32(Type *Ty, Value *Ptr, unsigned Idx0, unsigned Idx1,
1966 ConstantInt::get(Type::getInt32Ty(Context), Idx1)
1976 unsigned Idx1, const Twine &Name = "") {
1979 ConstantInt::get(Type::getInt32Ty(Context), Idx1)
2008 Value *CreateConstGEP2_64(Type *Ty, Value *Ptr, uint64_t Idx0, uint64_t Idx1,
2012 ConstantInt::get(Type::getInt64Ty(Context), Idx1)
2022 uint64_t Idx1, const Twine &Name = "") {
2025 ConstantInt::get(Type::getInt64Ty(Context), Idx1)
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp1459 for (auto [Idx1, Reg2] : SRM1) { in computeComposites()
1477 Idx1->addComposite(Idx2, Idx3, getHwModes())) { in computeComposites()
1479 if (!UserDefined.contains({Idx1, Idx2}) || in computeComposites()
1480 agree(compose(Idx1, Idx2), SubRegAction.at(Idx3))) in computeComposites()
1481 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() + in computeComposites()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp1891 unsigned Idx1; in getSubRegIdxs() local
1905 Idx1 = Idxs[0][Paired.Width - 1]; in getSubRegIdxs()
1909 Idx1 = Idxs[CI.Width][Paired.Width - 1]; in getSubRegIdxs()
1912 return {Idx0, Idx1}; in getSubRegIdxs()
H A DSIISelLowering.cpp7989 int Idx1 = SVN->getMaskElt(I + 1); in lowerVECTOR_SHUFFLE() local
7998 if (Idx1 >= SrcNumElts) { in lowerVECTOR_SHUFFLE()
8000 Idx1 -= SrcNumElts; in lowerVECTOR_SHUFFLE()
8004 int AlignedIdx1 = Idx1 & ~(NewSrcNumElts - 1); in lowerVECTOR_SHUFFLE()
8013 int NewMaskIdx1 = Idx1 - AlignedIdx1; in lowerVECTOR_SHUFFLE()
8030 const int Idx1 = SVN->getMaskElt(I + 1); in lowerVECTOR_SHUFFLE() local
8032 int VecIdx1 = Idx1 < SrcNumElts ? 0 : 1; in lowerVECTOR_SHUFFLE()
8034 int EltIdx1 = Idx1 < SrcNumElts ? Idx1 : Idx1 - SrcNumElts; in lowerVECTOR_SHUFFLE()
15462 SDValue Idx1 = Op1.getOperand(1); in performFMACombine() local
15483 if (Idx1 != Op2.getOperand(1) || Idx2 != FMAOp2.getOperand(1) || in performFMACombine()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h772 unsigned commuteOperandsForFold(MachineInstr &MI, unsigned Idx1) const;
H A DX86InstrInfo.cpp7403 unsigned Idx1) const { in commuteOperandsForFold()
7405 if (!findCommutedOpIndices(MI, Idx1, Idx2)) in commuteOperandsForFold()
7406 return Idx1; in commuteOperandsForFold()
7410 Register Reg1 = MI.getOperand(Idx1).getReg(); in commuteOperandsForFold()
7412 bool Tied1 = 0 == MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO); in commuteOperandsForFold()
7418 return Idx1; in commuteOperandsForFold()
7420 return commuteInstruction(MI, false, Idx1, Idx2) ? Idx2 : Idx1; in commuteOperandsForFold()
H A DX86ISelLowering.cpp41024 unsigned Idx1 = (M1 & 2) ? (SrcVT.getVectorNumElements() / 2) : 0; in canonicalizeShuffleMaskWithHorizOp() local
41026 SDValue V1 = extract128BitVector(BC[0].getOperand(M1 & 1), Idx1, DAG, DL); in canonicalizeShuffleMaskWithHorizOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVectorCombine.cpp2789 Value *Idx1 = Gep1->getOperand(1); in calculatePointerDifference() local
2793 Simplify(CallBuilder(B, CreateSub(Idx0, Idx1))))) in calculatePointerDifference()
2797 KnownBits Known1 = getKnownBits(Idx1, Gep1); in calculatePointerDifference()
2804 Value *AndU1 = Simplify(CallBuilder(B, CreateAnd(Idx1, MaskU))); in calculatePointerDifference()
2815 Value *AndK1 = Simplify(CallBuilder(B, CreateAnd(Idx1, MaskK))); in calculatePointerDifference()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstructionCombining.cpp3330 Value *Idx1, *Idx2; in visitGetElementPtrInst() local
3332 m_OneUse(m_AddLike(m_Value(Idx1), m_Value(Idx2))))) { in visitGetElementPtrInst()
3342 Idx1, "", NWFlags); in visitGetElementPtrInst()
3349 m_Value(Idx1), m_ConstantInt(C))))))) { in visitGetElementPtrInst()
3361 Builder.CreateSExt(Idx1, GEP.getOperand(1)->getType()), "", NWFlags); in visitGetElementPtrInst()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp3092 &TmpInputs, &BuildVector](ArrayRef<int> Mask, unsigned Idx1, in SplitVecRes_VECTOR_SHUFFLE()
3094 if (AccumulateResults(Idx1)) { in SplitVecRes_VECTOR_SHUFFLE()
3095 if (Inputs[Idx1]->getOpcode() == ISD::BUILD_VECTOR && in SplitVecRes_VECTOR_SHUFFLE()
3097 Output = BuildVector(Inputs[Idx1], Inputs[Idx2], Mask); in SplitVecRes_VECTOR_SHUFFLE()
3099 Output = DAG.getVectorShuffle(NewVT, DL, Inputs[Idx1], in SplitVecRes_VECTOR_SHUFFLE()
3102 if (TmpInputs[Idx1]->getOpcode() == ISD::BUILD_VECTOR && in SplitVecRes_VECTOR_SHUFFLE()
3104 Output = BuildVector(TmpInputs[Idx1], TmpInputs[Idx2], Mask); in SplitVecRes_VECTOR_SHUFFLE()
3106 Output = DAG.getVectorShuffle(NewVT, DL, TmpInputs[Idx1], in SplitVecRes_VECTOR_SHUFFLE()
3109 Inputs[Idx1] = Output; in SplitVecRes_VECTOR_SHUFFLE()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp460 [&](ArrayRef<int> RegMask, unsigned Idx1, unsigned Idx2, bool NewReg) { in costShuffleViaSplitting() argument
535 [&](ArrayRef<int> RegMask, unsigned Idx1, unsigned Idx2, bool NewReg) { in costShuffleViaVRegSplitting() argument
H A DRISCVISelLowering.cpp5447 [&](ArrayRef<int> SrcSubMask, unsigned Idx1, unsigned Idx2, bool NewReg) { in lowerShuffleViaVRegSplitting() argument
5450 Operands.back().emplace_back(Idx1, Idx2, SmallVector<int>(SrcSubMask)); in lowerShuffleViaVRegSplitting()
5493 const auto &[Idx1, Idx2, _] = Data[I]; in lowerShuffleViaVRegSplitting()
5499 SDValue &V = Values.try_emplace(Idx1).first->getSecond(); in lowerShuffleViaVRegSplitting()
5501 V = ExtractValue(Idx1 >= NumOfSrcRegs ? V2 : V1, in lowerShuffleViaVRegSplitting()
5502 (Idx1 % NumOfSrcRegs) * NumOpElts); in lowerShuffleViaVRegSplitting()
5511 for (const auto &[Idx1, Idx2, Mask] : Data) { in lowerShuffleViaVRegSplitting()
5512 SDValue V1 = Values.at(Idx1); in lowerShuffleViaVRegSplitting()
5515 Values[Idx1] = V; in lowerShuffleViaVRegSplitting()
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DExpr.cpp4277 auto Idx1 = Array1->getIdx(); in isSameComparisonOperand() local
4279 const auto Integer1 = dyn_cast<IntegerLiteral>(Idx1); in isSameComparisonOperand()
4286 if (!isSameComparisonOperand(Idx1, Idx2)) in isSameComparisonOperand()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DARM.cpp5959 llvm::Value *Idx1 = llvm::ConstantInt::get(SizeTy, 1); in EmitAArch64BuiltinExpr() local
5961 Value *Op1 = Builder.CreateExtractElement(Vec, Idx1, "lane1"); in EmitAArch64BuiltinExpr()
5971 llvm::Value *Idx1 = llvm::ConstantInt::get(SizeTy, 1); in EmitAArch64BuiltinExpr() local
5973 Value *Op1 = Builder.CreateExtractElement(Vec, Idx1, "lane1"); in EmitAArch64BuiltinExpr()
5983 llvm::Value *Idx1 = llvm::ConstantInt::get(SizeTy, 1); in EmitAArch64BuiltinExpr() local
5985 Value *Op1 = Builder.CreateExtractElement(Vec, Idx1, "lane1"); in EmitAArch64BuiltinExpr()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp2292 int Idx1 = Ex1Idx->getZExtValue(); in getShallowScore() local
2294 int Dist = Idx2 - Idx1; in getShallowScore()
6561 std::optional<unsigned> Idx1 = getElementIndex(IE1); in areTwoInsertFromSameBuildVector() local
6563 if (Idx1 == std::nullopt || Idx2 == std::nullopt) in areTwoInsertFromSameBuildVector()
6577 unsigned Idx1 = getElementIndex(IE1).value_or(*Idx2); in areTwoInsertFromSameBuildVector() local
6578 IsReusedIdx |= ReusedIdx.test(Idx1); in areTwoInsertFromSameBuildVector()
6579 ReusedIdx.set(Idx1); in areTwoInsertFromSameBuildVector()
6586 unsigned Idx2 = getElementIndex(IE2).value_or(*Idx1); in areTwoInsertFromSameBuildVector()
14407 unsigned Idx1 = *getElementIndex(IE1); in isFirstInsertElement() local
14420 getElementIndex(I2).value_or(Idx1) != Idx1) in isFirstInsertElement()