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Searched refs:IXGBE_WRITE_REG (Results 1 – 17 of 17) sorted by relevance

/freebsd/sys/dev/ixgbe/
H A Dixgbe_dcb_82599.c135 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); in ixgbe_dcb_config_rx_arbiter_82599()
147 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); in ixgbe_dcb_config_rx_arbiter_82599()
160 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); in ixgbe_dcb_config_rx_arbiter_82599()
168 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); in ixgbe_dcb_config_rx_arbiter_82599()
191 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); in ixgbe_dcb_config_tx_desc_arbiter_82599()
192 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0); in ixgbe_dcb_config_tx_desc_arbiter_82599()
208 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg); in ixgbe_dcb_config_tx_desc_arbiter_82599()
216 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg); in ixgbe_dcb_config_tx_desc_arbiter_82599()
246 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg); in ixgbe_dcb_config_tx_data_arbiter_82599()
258 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg); in ixgbe_dcb_config_tx_data_arbiter_82599()
[all …]
H A Dixgbe_dcb_82598.c121 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
131 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
143 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); in ixgbe_dcb_config_rx_arbiter_82598()
150 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); in ixgbe_dcb_config_rx_arbiter_82598()
155 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); in ixgbe_dcb_config_rx_arbiter_82598()
186 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); in ixgbe_dcb_config_tx_desc_arbiter_82598()
201 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); in ixgbe_dcb_config_tx_desc_arbiter_82598()
230 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
244 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
250 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
[all …]
H A Dixgbe_82598.c109 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); in ixgbe_set_pcie_completion_timeout()
271 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval); in ixgbe_start_hw_82598()
279 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_82598()
519 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg); in ixgbe_fc_enable_82598()
520 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg); in ixgbe_fc_enable_82598()
528 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl); in ixgbe_fc_enable_82598()
529 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth); in ixgbe_fc_enable_82598()
531 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); in ixgbe_fc_enable_82598()
532 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); in ixgbe_fc_enable_82598()
540 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_fc_enable_82598()
[all …]
H A Dixgbe_common.c355 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); in ixgbe_setup_fc_generic()
362 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); in ixgbe_setup_fc_generic()
418 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); in ixgbe_start_hw_generic()
467 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); in ixgbe_start_hw_gen2()
468 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); in ixgbe_start_hw_gen2()
476 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); in ixgbe_start_hw_gen2()
483 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_gen2()
1128 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); in ixgbe_stop_adapter_generic()
1135 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); in ixgbe_stop_adapter_generic()
1142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); in ixgbe_stop_adapter_generic()
[all …]
H A Dif_sriov.c253 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf->pool), vmolr); in ixgbe_vf_set_default_vlan()
254 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf->pool), vmvir); in ixgbe_vf_set_default_vlan()
341 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vf_index), vfte); in ixgbe_vf_enable_transmit()
359 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vf_index), vfre); in ixgbe_vf_enable_receive()
445 IXGBE_WRITE_REG(&sc->hw, IXGBE_MTA(vec_reg), mta_reg); in ixgbe_vf_set_mc_addr()
449 IXGBE_WRITE_REG(&sc->hw, IXGBE_VMOLR(vf->pool), vmolr); in ixgbe_vf_set_mc_addr()
519 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); in ixgbe_vf_set_lpe()
742 IXGBE_WRITE_REG(hw, IXGBE_VFRE(pf_reg), IXGBE_VF_BIT(sc->pool)); in ixgbe_if_iov_uninit()
743 IXGBE_WRITE_REG(hw, IXGBE_VFTE(pf_reg), IXGBE_VF_BIT(sc->pool)); in ixgbe_if_iov_uninit()
749 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vf_reg), 0); in ixgbe_if_iov_uninit()
[all …]
H A Dixgbe_82599.c135 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_init_phy_ops_82599()
201 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); in ixgbe_setup_sfp_modules_82599()
300 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); in prot_autoc_write_82599()
622 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); in ixgbe_stop_mac_link_on_d3_82599()
712 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); in ixgbe_disable_tx_laser_multispeed_fiber()
731 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); in ixgbe_enable_tx_laser_multispeed_fiber()
788 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); in ixgbe_set_hard_rate_select_speed()
1113 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); in ixgbe_reset_hw_82599()
1152 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); in ixgbe_reset_hw_82599()
1187 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); in ixgbe_reset_hw_82599()
[all …]
H A Dif_ix.c654 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); in ixgbe_initialize_rss_mapping()
656 IXGBE_WRITE_REG(hw, in ixgbe_initialize_rss_mapping()
664 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), rss_key[i]); in ixgbe_initialize_rss_mapping()
703 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); in ixgbe_initialize_rss_mapping()
736 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); in ixgbe_initialize_receive_units()
744 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg); in ixgbe_initialize_receive_units()
757 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), in ixgbe_initialize_receive_units()
759 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); in ixgbe_initialize_receive_units()
760 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), in ixgbe_initialize_receive_units()
783 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(j), srrctl); in ixgbe_initialize_receive_units()
[all …]
H A Dif_ixv.c649 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_EICS_RTX_QUEUE); in ixv_if_init()
652 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(sc->vector), IXGBE_LINK_ITR); in ixv_if_init()
685 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask); in ixv_enable_queue()
699 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, mask); in ixv_disable_queue()
733 IXGBE_WRITE_REG(hw, IXGBE_VTEICR, reg); in ixv_msix_mbx()
739 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_EIMS_OTHER); in ixv_msix_mbx()
1253 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(j), txdctl); in ixv_initialize_transmit_units()
1256 IXGBE_WRITE_REG(&sc->hw, IXGBE_VFTDH(j), 0); in ixv_initialize_transmit_units()
1257 IXGBE_WRITE_REG(&sc->hw, IXGBE_VFTDT(j), 0); in ixv_initialize_transmit_units()
1273 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(j), in ixv_initialize_transmit_units()
[all …]
H A Dixgbe_vf.c38 #define IXGBE_VFWRITE_REG IXGBE_WRITE_REG
117 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0); in ixgbe_virt_clr_reg()
120 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0); in ixgbe_virt_clr_reg()
121 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0); in ixgbe_virt_clr_reg()
122 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0); in ixgbe_virt_clr_reg()
123 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl); in ixgbe_virt_clr_reg()
124 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0); in ixgbe_virt_clr_reg()
125 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0); in ixgbe_virt_clr_reg()
126 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0); in ixgbe_virt_clr_reg()
127 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0); in ixgbe_virt_clr_reg()
[all …]
H A Dixgbe_x540.c239 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); in ixgbe_reset_hw_X540()
269 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); in ixgbe_reset_hw_X540()
703 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); in ixgbe_update_flash_X540()
716 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); in ixgbe_update_flash_X540()
804 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), in ixgbe_acquire_swfw_sync_X540()
829 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); in ixgbe_acquire_swfw_sync_X540()
878 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); in ixgbe_release_swfw_sync_X540()
958 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); in ixgbe_release_swfw_sync_semaphore()
962 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); in ixgbe_release_swfw_sync_semaphore()
1026 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); in ixgbe_blink_led_start_X540()
[all …]
H A Dixgbe_mbx.c437 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, vf_mailbox); in ixgbe_obtain_mbx_lock_vf()
486 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, vf_mailbox); in ixgbe_release_mbx_lock_vf()
526 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_REQ); in ixgbe_write_mbx_vf_legacy()
570 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, vf_mailbox); in ixgbe_write_mbx_vf()
609 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_ACK); in ixgbe_read_mbx_vf_legacy()
650 IXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, vf_mailbox); in ixgbe_read_mbx_vf()
732 IXGBE_WRITE_REG(hw, IXGBE_PFMBICR(index), in ixgbe_clear_msg_pf()
747 IXGBE_WRITE_REG(hw, IXGBE_PFMBICR(index), in ixgbe_clear_ack_pf()
840 IXGBE_WRITE_REG(hw, IXGBE_PFVFLREC(index), (1 << vf_shift)); in ixgbe_check_for_rst_pf()
870 IXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_id), pf_mailbox); in ixgbe_obtain_mbx_lock_pf()
[all …]
H A Dixgbe_phy.c608 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); in ixgbe_read_phy_reg_mdi()
639 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); in ixgbe_read_phy_reg_mdi()
711 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); in ixgbe_write_phy_reg_mdi()
719 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); in ixgbe_write_phy_reg_mdi()
748 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); in ixgbe_write_phy_reg_mdi()
2303 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); in ixgbe_i2c_stop()
2357 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); in ixgbe_clock_out_i2c_byte()
2383 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); in ixgbe_get_i2c_ack()
2432 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); in ixgbe_clock_in_i2c_bit()
2504 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); in ixgbe_raise_i2c_clk()
[all …]
H A Dixgbe_x550.c335 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_setup_mux_ctl()
890 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); in ixgbe_dmac_config_X550()
916 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); in ixgbe_dmac_config_X550()
973 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); in ixgbe_dmac_config_tcs_X550()
993 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); in ixgbe_dmac_update_tcs_X550()
1000 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); in ixgbe_dmac_update_tcs_X550()
1060 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); in ixgbe_set_source_address_pruning_X550()
1061 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); in ixgbe_set_source_address_pruning_X550()
1086 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_ethertype_anti_spoofing_X550()
1149 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); in ixgbe_write_iosf_sb_reg_x550()
[all …]
H A Dixgbe_common.h41 IXGBE_WRITE_REG(hw, reg, (u32) value); \
42 IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
H A Dif_fdir.c65 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); in ixgbe_reinit_fdir()
H A Dix_txrx.c260 IXGBE_WRITE_REG(&sc->hw, txr->tail, pidx); in ixgbe_isc_txd_flush()
356 IXGBE_WRITE_REG(&sc->hw, rxr->tail, pidx); in ixgbe_isc_rxd_flush()
H A Dixgbe_osdep.h215 #define IXGBE_WRITE_REG(a, reg, val) ixgbe_write_reg(a, reg, val) macro