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Searched refs:INSERT_VECTOR_ELT (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp712 if (ISD == ISD::INSERT_VECTOR_ELT) { in getVectorInstrCost()
741 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
752 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
760 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
H A DPPCISelLowering.cpp871 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in PPCTargetLowering()
954 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in PPCTargetLowering()
1203 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in PPCTargetLowering()
1204 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in PPCTargetLowering()
1312 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
1313 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
1314 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
1315 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
1317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in PPCTargetLowering()
1318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in PPCTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h538 INSERT_VECTOR_ELT, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp432 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
436 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
H A DLegalizeVectorTypes.cpp66 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
1091 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
1917 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
1921 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
4326 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
4715 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, in CollectOpsToWiden()
5650 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
7200 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE()
7237 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE_SEQ()
7388 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, d in BuildVectorFromScalar()
[all...]
H A DSelectionDAGDumper.cpp324 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; in getOperationName()
H A DLegalizeDAG.cpp3471 case ISD::INSERT_VECTOR_ELT: in ExpandNode()
5091 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { in PromoteNode()
5667 case ISD::INSERT_VECTOR_ELT: { in PromoteNode()
5710 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT, in PromoteNode()
H A DLegalizeIntegerTypes.cpp136 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerResult()
1929 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerOperand()
5265 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; in ExpandIntegerOperand()
6031 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, in PromoteIntRes_INSERT_VECTOR_ELT()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp148 setOperationAction(ISD::INSERT_VECTOR_ELT, in R600TargetLowering()
202 ISD::SELECT_CC, ISD::INSERT_VECTOR_ELT, ISD::LOAD}); in R600TargetLowering()
402 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
663 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1761 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
H A DSIISelLowering.cpp329 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
359 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
360 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
373 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
374 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v6i32); in SITargetLowering()
387 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
388 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v8i32); in SITargetLowering()
401 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
402 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v16i32); in SITargetLowering()
415 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp318 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
335 setOperationAction(ISD::INSERT_VECTOR_ELT, LegalPackedVT, Custom); in initVPUActions()
1839 return CDAG.getNode(ISD::INSERT_VECTOR_ELT, ResultVT, {AccuV, ElemV, IdxV}); in lowerBUILD_VECTOR()
1915 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
3165 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); in lowerINSERT_VECTOR_ELT()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp249 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in LoongArchTargetLowering()
295 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in LoongArchTargetLowering()
420 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
1438 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()
4185 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), N->getValueType(0), in performINTRINSIC_WO_CHAINCombine()
4190 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), N->getValueType(0), in performINTRINSIC_WO_CHAINCombine()
4195 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), N->getValueType(0), in performINTRINSIC_WO_CHAINCombine()
4199 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), N->getValueType(0), in performINTRINSIC_WO_CHAINCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp182 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
264 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
343 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
344 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom); in addMVEVectorTypes()
409 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
458 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
1034 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, in ARMTargetLowering()
2246 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
2260 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
4580 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue, in LowerFormalArguments()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp151 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::f16, Custom); in initializeHVXLowering()
233 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
390 setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
1787 SDValue T0 = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in LowerHvxInsertElement()
3207 case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1663 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, in HexagonTargetLowering()
1712 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
3366 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp227 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1476 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
2292 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp326 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAIntType()
380 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
1957 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2520 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp426 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
564 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in SystemZTargetLowering()
565 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in SystemZTargetLowering()
5827 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], in buildVector()
5899 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, in lowerSCALAR_TO_VECTOR()
5929 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, in lowerINSERT_VECTOR_ELT()
6221 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
7520 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) { in combineBSWAP()
7545 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VecVT, in combineBSWAP()
H A DSystemZISelDAGToDAG.cpp1725 case ISD::INSERT_VECTOR_ELT: { in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp495 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Expand); in NVPTXTargetLowering()
508 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2bf16, Expand); in NVPTXTargetLowering()
519 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Expand); in NVPTXTargetLowering()
524 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom); in NVPTXTargetLowering()
2769 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp982 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in X86TargetLowering()
1144 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in X86TargetLowering()
1145 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in X86TargetLowering()
1146 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in X86TargetLowering()
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in X86TargetLowering()
1185 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1647 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1751 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
2012 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
2140 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1114 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, in AArch64TargetLowering()
1528 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in AArch64TargetLowering()
1866 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
2076 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Default); in addTypeForFixedLengthSVE()
6678 DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, XVT, DAG.getUNDEF(XVT), X, Zero); in LowerFLDEXP()
6679 SDValue VExp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ExpVT, in LowerFLDEXP()
6856 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
12773 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Input.getValueType(), OpLHS, in GeneratePerfectShuffle()
13283 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()
14220 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp733 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
757 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT, in RISCVTargetLowering()
859 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT, in RISCVTargetLowering()
977 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, VT, in RISCVTargetLowering()
1160 setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
1356 ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, in RISCVTargetLowering()
1500 ISD::INSERT_VECTOR_ELT, ISD::ABS}); in RISCVTargetLowering()
3598 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, in lowerBuildVectorViaDominantValues()
3654 // If we have to use more than one INSERT_VECTOR_ELT then this in lowerBuildVectorOfConstants()
3812 SDValue Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, D in lowerBuildVectorOfConstants()
[all...]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td488 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
795 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1821 case InsertElement: return ISD::INSERT_VECTOR_ELT; in InstructionOpcodeToISD()

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