| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDKernelCodeTUtils.cpp | 384 MCConstantExpr::create(Hi_32(compute_pgm_resource_registers), Ctx); in initDefault()
484 OS.emitIntValue(Hi_32(compute_pgm_resource_registers), in EmitKernelCodeT()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 197 unsigned UpperTrailingOnes = llvm::countr_one(Hi_32(Val)); in extractRotateInfo()
529 if (STI.hasFeature(RISCV::FeatureStdExtZba) && Lo_32(Val) == Hi_32(Val)) { in generateTwoRegInstSeq()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCInstructionSelector.cpp | 278 uint32_t HiTZ = llvm::countr_zero<uint32_t>(Hi_32(Imm)); in findContiguousZerosAtLeast()
296 uint32_t Hi32 = Hi_32(Imm); in selectI64ImmDirect()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEFrameLowering.cpp | 260 .addImm(Hi_32(NumBytes)); in emitSPAdjustment()
|
| H A D | VERegisterInfo.cpp | 214 .addImm(Hi_32(Offset)); in prepareReplaceFI()
|
| H A D | VEInstrInfo.td | 60 return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()),
77 return CurDAG->getTargetConstant(Hi_32(getFpImmVal(N)), SDLoc(N), MVT::i32);
|
| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | APInt.cpp | 1383 borrow = Hi_32(p) - Hi_32(subres); in KnuthDiv()
1490 U[i * 2 + 1] = Hi_32(tmp); in divide()
1499 V[i * 2 + 1] = Hi_32(tmp); in divide()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.cpp | 463 Imm = Hi_32(Imm); in encodeInstruction()
|
| H A D | AMDGPUInstPrinter.cpp | 88 O << formatHex(static_cast<uint64_t>(Hi_32(Imm))); in printFP64ImmOperand()
625 O << formatHex(static_cast<uint64_t>(Hi_32(Imm))); in printImmediate64()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | MathExtras.h | 155 constexpr uint32_t Hi_32(uint64_t Value) { in Hi_32() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 428 CurDAG->getTargetConstant(Hi_32(Imm), DL, MVT::i32)); in buildSMovImm64()
1818 getMaterializedScalarImm32(Hi_32(RemainderOffset), DL); in SelectFlatOffsetImpl()
1923 !TII->isInlineConstant(APInt(32, Hi_32(COffsetVal))); in SelectGlobalSAddr()
|
| H A D | SIFrameLowering.cpp | 883 .addImm(Hi_32(Rsrc23)) in emitEntryFunctionScratchRsrcRegSetup()
|
| H A D | AMDGPUInstructionSelector.cpp | 5450 !TII.isInlineConstant(APInt(32, Hi_32(ConstOffset))); in selectGlobalSAddr()
6082 return buildRSRC(B, MRI, 0, Hi_32(DefaultFormat), BasePtr); in buildAddr64RSrc()
6091 return buildRSRC(B, MRI, -1, Hi_32(DefaultFormat), BasePtr); in buildOffsetSrc()
|
| H A D | AMDGPUISelLowering.cpp | 5330 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
5340 DAG.getConstant(Hi_32(CVal), SL, MVT::i32)); in PerformDAGCombine()
|
| H A D | SIInstrInfo.cpp | 3477 return Hi_32(Imm); in extractSubregFromImm()
6847 .addImm(Hi_32(RsrcDataFormat)); in extractRsrcPtr()
|
| H A D | SIISelLowering.cpp | 12152 uint32_t ValHi = Hi_32(Val); in splitBinaryBitConstantOp()
14487 if (!Const || Hi_32(Const->getZExtValue()) != uint32_t(-1)) in tryFoldMADwithSRL()
14651 SDValue ConstHi32 = DAG.getConstant(Hi_32(Val), SL, MVT::i32); in foldAddSub64WithZeroLowBitsTo32()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 663 return isInt<8>(Lo_32(V)) && isInt<8>(Hi_32(V)); in isSmallConstant()
|
| H A D | HexagonBitSimplify.cpp | 1436 unsigned Lo = Lo_32(C), Hi = Hi_32(C); in genTfrConst()
|
| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | XCOFFObjectWriter.cpp | 878 W.write<uint32_t>(Hi_32(SectionOrLength)); in writeSymbolAuxCsectEntry()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3362 if ((Hi_32(ImmOp64) & 0x7ff00000) == 0) { in convertIntToDoubleImm()
3464 if (loadImmediate(Hi_32(ImmOp64), FirstReg, MCRegister(), true, false, in expandLoadDoubleImmToGPR()
3529 !((Hi_32(ImmOp64) & 0xffff0000) && (Hi_32(ImmOp64) & 0x0000ffff))) { in expandLoadDoubleImmToFPR()
3539 loadImmediate(Hi_32(ImmOp64), TmpReg, MCRegister(), true, false, IDLoc, in expandLoadDoubleImmToFPR()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 1011 unsigned HiTZ = llvm::countr_zero<uint32_t>(Hi_32(Imm)); in findContiguousZerosAtLeast()
1025 unsigned Hi32 = Hi_32(Imm); in selectI64ImmDirect()
1266 unsigned Hi32 = Hi_32(Imm); in selectI64ImmDirectPrefix()
1423 uint32_t Hi16OfHi32 = (Hi_32(Imm) >> 16) & 0xffff; in selectI64Imm()
1424 uint32_t Lo16OfHi32 = Hi_32(Imm) & 0xffff; in selectI64Imm()
|
| H A D | PPCISelLowering.cpp | 9687 uint32_t Hi = Hi_32(APSplatBits.getZExtValue()); in LowerBUILD_VECTOR()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1637 int s8 = Hi_32(Value); in processInstruction()
|
| /freebsd/contrib/llvm-project/llvm/lib/Support/Windows/ |
| H A D | Path.inc | 884 Hi_32(Size), Lo_32(Size), 0);
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 5053 Value = Hi_32(Value); in validateVOPLiteral()
|